4选1数据选择器.vhd

Altera FPGA工程师成长手册源文件清华大学

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX4_1 IS
PORT(a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
      d0,d1,d2,d3:IN STD_LOGIC;
                g: IN STD_LOGIC;
                    y:OUT STD_LOGIC);
END MUX4_1;
ARCHITECTURE eight OF MUX4_1 IS
BEGIN
PROCESS(a,g,d0,d1,d2,d3) 
BEGIN
	IF g='0' THEN y<='0';
	ELSE
	CASE a IS
		WHEN "00"=>y<=d0;
		WHEN "01"=>y<=d1;
		WHEN "10"=>y<=d2;
		WHEN "11"=>y<=d3;
	     WHEN others=>y<='0';
	END CASE;
	END IF;
END PROCESS;
END eight ;