有限状态机.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 50 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY machine_name IS
	PORT
	(   CLK: IN	STD_LOGIC;                   
		? : IN	STD_LOGIC;                            //?这里表示需添加自己定义的端口
		?: IN	STD_LOGIC;
		?: OUT	STD_LOGIC
	);
END machine_name;

ARCHITECTURE a OF machine_name IS
	TYPE STATE_TYPE IS (state_name_0, __state_name_1, …__state_name_n);状态定义
	SIGNAL CURRENT_STATE,NEXT_STATE：STATES;	//定义当前状态和下一状态
BEGIN
P1:	PROCESS(CURRENT_STATE,STATE_INPUTS)
	BEGIN
         	CASE CURRENT_STATE IS
			WHEN ?? =>???
				IF  ??? THEN  ???  
                      NEXT_STATE<=????;
                   ELSE
                       NEXT_STATE<=????;
                       ???;
					END IF;

				WHEN ?? =>???
				     IF  ??? THEN  ???  
                           NEXT_STATE<=????;
                        ELSE
                            NEXT_STATE<=????;
                            ???;
					END IF;

WHEN OTHERS =>
				     NEXT_STATE<=????;
                   
			END CASE;
		END IF;
	END PROCESS;
P2:  ROCESS (RESET,CLK) 						//时序逻辑进程,每个时钟上升沿更新进程
     BEGIN
        IF RESET='1' THEN   //状态机复位
           CURRENT_STATE<=  state_preset;          	//异步复位
        ELSIF (CLK='1' AND CLK' EVENT) THEN
           CURRENT_STATE<=NEXT_STATE; 			//当测到时钟上升沿时转换至下一状态
        END IF;
    END PROCESS; 
END a;