加法计数器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER_12 IS
    PORT(CLK,CLR,EN：IN STD_LOGIC;
          Q1,Q2,Q3,Q4：OUT STD_LOGIC;
    END COUNTER_12;
ARCHITECTURE ART OF COUNTER_12 IS
SIGNAL  COUNTER: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    Q1<= COUNTER (0);
Q2<= COUNTER (1);
Q3<= COUNTER (2);
Q4<= COUNTER (3); 
PROCESS(CLK,CLR)
BEGIN
IF(CLR='0')THEN      				        //CLR优先级最高，放在外层
COUNTER <="0000";
ELSIF(CLK'EVENT AND CLK='1')THEN    	   //CLK放在这里表示内层都要被它同步
IF(EN='1')THEN      	
  IF(COUNTER <="1011")THEN
     COUNTER <="0000";
ELSE                          	
       COUNTER <= COUNTER +1;
          END IF;
       END IF;
END IF;
   END PROCESS;
END ART;