8位的移位寄存器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFTER IS
PORT(DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SHIFT_LEFT:IN STD_LOGIC;
SHIFT_RIGHT:IN STD_LOGIC;
RESET:IN STD_LOGIC;
MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
QOUT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0));
END SHIFTER;
ARCHITECTURE ART OF SHIFTER IS
BEGIN
PROCESS 
BEGIN
WAIT UNTIL(RISING_EDGE(CLK));
IF(RESET='1')THEN
    QOUT<="00000000";    		--同步复位功能的实现
ELSE					
CASE MODE IS
WHEN "01"=>QOUT<=SHIFT_RIGHT & QOUT(7 DOWNTO 1);		--右移一位
WHEN "10"=>QOUT<=QOUT(6 DOWNTO 0)&SHIFT_LEFT;      --左移一位					
WHEN "11"=>QOUT<=DATA;                                 --置数功能
WHEN OTHERS=>NULL;
  END CASE;
END IF;
END PROCESS;
END ART;