8位锁存器.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LATCH_8 IS 
   PORT(D:IN STD_LOGIC_VECTOR(0 TO 7);
         OE:IN STD_LOGIC;
G:IN STD_LOGIC;
         Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END LATCH_8; 
ARCHITECTURE ART OF LATCH_8 IS
SIGNAL Q_TEMP:STD_LOGIC_VECTOR(0 TO 7);
BEGIN
PROCESS(G,OE,D)
BEGIN
    IF OE='0' THEN
       IF G='1' THEN
  Q_TEMP <=D;
       END IF;
       ELSE Q_TEMP <="ZZZZZZZZ";
END IF;
END PROCESS;
    Q <= Q_TEMP;
END ART;