add4.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADD4 IS
PORT (A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           CIN: IN STD_LOGIC;
           SUM:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           COUNT: OUT STD_LOGIC);
END ADD4;
ARCHITECTURE ART OF ADD4 IS
SIGNAL A1,B1,C :STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN 
A1<='0'&A;
B1<='0'&B;
    PROCESS(A1,B1,CIN,C)
    BEGIN
        C<=A1+B1+CIN;
END PROCESS;
SUM<=C(3 DOWNTO 0);
COUNT<=C(4);
END ART;