cnt4.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT (CLK:IN STD_LOGIC;
   EN: IN STD_LOGIC;
   RST: IN STD_LOGIC;
   Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END CNT4;
ARCHITECTURE  ART OF CNT4 IS
  SIGNAL CNT: STD_LOGIC_VECTOR(3 DOWNTO 0);
   BEGIN
  PROCESS(CLK,EN,RST)
     BEGIN
        IF RST='1' THEN CNT<="0000";
        ELSIF CLK'EVENT AND CLK='1' THEN
            IF EN='1' THEN 
             IF CNT<9 THEN  CNT<=CNT+1;
             ELSE CNT<="0000";
             END IF;
     END IF;
  END IF;
END PROCESS;
Q<=CNT;
END ART;