seg_7.vhd

来自「Altera FPGA工程师成长手册源文件清华大学」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SEG_7 IS
PORT (SEG: IN STD_LOGIC_VECTOR(3 DOWNTO 0 );   //四位二进制码输入
        Q3: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );//输出LED七段码
END SEG_7;
ARCHITECTURE ART OF SEG_7 IS
BEGIN
PROCESS(SEG)
    BEGIN
CASE SEG IS
WHEN "0000" => Q3<="0000001";   
WHEN "0001" => Q3<="1001111";
WHEN "0010" => Q3<="0010010";
WHEN "0011" => Q3<="0000110";
WHEN "0100" => Q3<="1001100";
WHEN "0101" => Q3<="0100100";
WHEN "0110" => Q3<="0100000";
WHEN "0111" => Q3<="0001111";
WHEN "1000" => Q3<="0000000";
WHEN "1001" => Q3<="0000100";
WHEN OTHERS => Q3<="1111111";
END CASE;
END PROCESS; 
END ART;