📄 bulkloop.lst
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C51 COMPILER V6.10 BULKLOOP 03/19/2007 15:27:12 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE BULKLOOP
OBJECT MODULE PLACED IN .\bulkloop.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE .\bulkloop.c DEBUG OBJECTEXTEND
stmt level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: bulkloop.c
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // Copyright (c) 2000 Cypress Semiconductor All rights reserved
7 //-----------------------------------------------------------------------------
8 #include "fx2.h"
9 #include "fx2regs.h"
10 #include "fx2sdly.h" // SYNCDELAY macro
11
12 extern BOOL GotSUD; // Received setup data flag
13 extern BOOL Sleep;
14 extern BOOL Rwuen;
15 extern BOOL Selfpwr;
16
17 BYTE Configuration; // Current configuration
18 BYTE AlternateSetting; // Alternate settings
19
20 #define VR_NAKALL_ON 0xD0
21 #define VR_NAKALL_OFF 0xD1
22
23 //-----------------------------------------------------------------------------
24 // Task Dispatcher hooks
25 // The following hooks are called by the task dispatcher.
26 //-----------------------------------------------------------------------------
27
28 void TD_Init(void) // Called once at startup
29 {
30 1 // set the CPU clock to 48MHz
31 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
32 1
33 1 // set the slave FIFO interface to 48MHz
34 1 IFCONFIG |= 0x40;
35 1
36 1 // Registers which require a synchronization delay, see section 15.14
37 1 // FIFORESET FIFOPINPOLAR
38 1 // INPKTEND OUTPKTEND
39 1 // EPxBCH:L REVCTL
40 1 // GPIFTCB3 GPIFTCB2
41 1 // GPIFTCB1 GPIFTCB0
42 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
43 1 // EPxFIFOCFG EPxGPIFFLGSEL
44 1 // PINFLAGSxx EPxFIFOIRQ
45 1 // EPxFIFOIE GPIFIRQ
46 1 // GPIFIE GPIFADRH:L
47 1 // UDMACRCH:L EPxGPIFTRIG
48 1 // GPIFTRIG
49 1
50 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
51 1 // ...these have been replaced by GPIFTC[B3:B0] registers
52 1
53 1 // default: all endpoints have their VALID bit set
54 1 // default: TYPE1 = 1 and TYPE0 = 0 --> BULK
55 1 // default: EP2 and EP4 DIR bits are 0 (OUT direction)
C51 COMPILER V6.10 BULKLOOP 03/19/2007 15:27:12 PAGE 2
56 1 // default: EP6 and EP8 DIR bits are 1 (IN direction)
57 1 // default: EP2, EP4, EP6, and EP8 are double buffered
58 1 //
59 1 // we are just using the default values, yes this is not necessary...
60 1 EP1OUTCFG = 0xA0;
61 1 // SYNCDELAY;
62 1 EP1INCFG = 0xA3;
63 1 // SYNCDELAY; // see TRM section 15.14
64 1 //EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0
65 1 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
66 1 SYNCDELAY;
67 1 EP4CFG = 0x00; // EP4 not valid
68 1 SYNCDELAY;
69 1 EP6CFG = 0xE0; // EP6 not valid
70 1 SYNCDELAY;
71 1 EP8CFG = 0x00; // EP8 not valid
72 1 SYNCDELAY;
73 1
74 1 EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
75 1 SYNCDELAY;
76 1 EP2BCL = 0x80;
77 1 SYNCDELAY;
78 1
79 1
80 1 OEA = 0xff; //A端口输出使能
81 1 IOA = 0x00; //输出电平
82 1 OEB = 0xff; //B端口
83 1 IOB = 0x00; //
84 1 OED = 0xff; //D端口
85 1 IOD = 0x00; //
86 1
87 1
88 1
89 1 Rwuen = TRUE; // Enable remote-wakeup
90 1 }
91
92
93 void TD_Poll(void) // Called repeatedly while the device is idle
94 {
95 1
96 1 IOA^=0xff;
97 1 IOB^=0xff;
98 1 IOD^=0xff;
99 1 EZUSB_Delay (1); //在一段时间后输出翻转
100 1
101 1 }
102
103 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
104 {
105 1 return(TRUE);
106 1 }
107
108 BOOL TD_Resume(void) // Called after the device resumes
109 {
110 1 return(TRUE);
111 1 }
112
113 //-----------------------------------------------------------------------------
114 // Device Request hooks
115 // The following hooks are called by the end point 0 device request parser.
116 //-----------------------------------------------------------------------------
117
C51 COMPILER V6.10 BULKLOOP 03/19/2007 15:27:12 PAGE 3
118 BOOL DR_GetDescriptor(void)
119 {
120 1 return(TRUE);
121 1 }
122
123 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
124 {
125 1 Configuration = SETUPDAT[2];
126 1 return(TRUE); // Handled by user code
127 1 }
128
129 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
130 {
131 1 EP0BUF[0] = Configuration;
132 1 EP0BCH = 0;
133 1 EP0BCL = 1;
134 1 return(TRUE); // Handled by user code
135 1 }
136
137 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
138 {
139 1 AlternateSetting = SETUPDAT[2];
140 1 return(TRUE); // Handled by user code
141 1 }
142
143 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
144 {
145 1 EP0BUF[0] = AlternateSetting;
146 1 EP0BCH = 0;
147 1 EP0BCL = 1;
148 1 return(TRUE); // Handled by user code
149 1 }
150
151 BOOL DR_GetStatus(void)
152 {
153 1 return(TRUE);
154 1 }
155
156 BOOL DR_ClearFeature(void)
157 {
158 1 return(TRUE);
159 1 }
160
161 BOOL DR_SetFeature(void)
162 {
163 1 return(TRUE);
164 1 }
165
166
167 #define VX_B2 0xB2 // get ENP2 CFG
168 #define VX_B3 0xB3 // get ENP4 CFG
169 #define VX_B4 0xB4 // get ENP6 CFG
170 #define VX_B5 0xB5 // get ENP8 CFG
171 #define VX_B6 0xB6 // get status
172 //#define VX_B6 0xB6 //get ENP2 CFG
173
174
175 BOOL DR_VendorCmnd(void)
176 {
177 1 BYTE tmp;
178 1
179 1 switch (SETUPDAT[1])
C51 COMPILER V6.10 BULKLOOP 03/19/2007 15:27:12 PAGE 4
180 1 {
181 2 case VX_B2:
182 2 EP0BUF[0] = VX_B2;
183 2 SYNCDELAY;
184 2 EP0BUF[1] = EP2CFG;
185 2 SYNCDELAY;
186 2 EP0BCH = 0;
187 2 EP0BCL = 2;
188 2 EP0CS |= bmHSNAK;
189 2 break;
190 2 case VX_B3:
191 2 EP0BUF[0] = VX_B3;
192 2 SYNCDELAY;
193 2 EP0BUF[1] = EP4CFG;
194 2 SYNCDELAY;
195 2 EP0BCH = 0;
196 2 EP0BCL = 2;
197 2 EP0CS |= bmHSNAK;
198 2 break;
199 2 case VX_B4:
200 2 EP0BUF[0] = VX_B4;
201 2 SYNCDELAY;
202 2 EP0BUF[1] = EP6CFG;
203 2 SYNCDELAY;
204 2 EP0BCH = 0;
205 2 EP0BCL = 2;
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