📄 stm32_init.c
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// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o25.7> TIM2_SMCR.MSM: Delay trigger input
// <o25.4..6> TIM2_SMCR.TS: Trigger Selection
// <i> Default: TIM1 (ITR0)
// <0=> TIM1 (ITR0)
// <1=> TIM2 (ITR1)
// <2=> TIM3 (ITR2)
// <3=> TIM4 (ITR3)
// <4=> TI1 Edge Detector (TI1F_ED)
// <5=> Filtered Timer Input 1 (TI1FP1)
// <6=> Filtered Timer Input 2 (TI1FP2)
// <7=> External Trigger Input (ETRF)
// <o25.0..2> TIM2_SMCR.SMS: Slave mode selection
// <i> Default: Slave mode disabled
// <0=> Slave mode disabled
// <1=> Encoder mode 1
// <2=> Encoder mode 2
// <3=> Encoder mode 3
// <4=> Reset mode
// <5=> Gated mode
// <6=> Trigger mode
// <7=> External clock mode 1
// </h>
//
//
//--------------------------------------------------------------------------- Timer 2 channel 1
// <h> Channel 1 Configuration
// <h> Cannel configured as output
// <o26.7> TIM2_CCMR1.OC1CE: Output Compare 1 Clear enabled
// <o26.4..6> TIM2_CCMR1.OC1M: Output Compare 1 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 1 to active level on match
// <2=> Set channel 1 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o26.3> TIM2_CCMR1.OC1PE: Output Compare 1 Preload enabled
// <o26.2> TIM2_CCMR1.OC1FE: Output Compare 1 Fast enabled
// <o26.0..1> TIM2_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <o28.1> TIM2_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: OC1 active high
// <0=> OC1 active high
// <1=> OC1 active low
// <o28.0> TIM1_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: OC1 not active
// <0=> OC1 not active
// <1=> OC1 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o26.4..7> TIM2_CCMR1.IC1F: Input Capture 1 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o26.2..3> TIM2_CCMR1.IC1PSC: Input Capture 1 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o26.0..1> TIM2_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <1=> CC1 configured as input, IC1 mapped on TI1
// <2=> CC1 configured as input, IC1 mapped on TI2
// <3=> CC1 configured as input, IC1 mapped on TRGI
// <o28.1> TIM2_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o28.0> TIM2_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o29> TIM2_CCR1: Capture/compare register 1 <0-65535>
// <i> Set the Compare register value for compare register 1.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 2 channel 2
// <h> Channel 2 Configuration
// <h> Cannel configured as output
// <o26.15> TIM2_CCMR1.OC2CE: Output Compare 2 Clear enabled
// <o26.12..14> TIM2_CCMR1.OC2M: Output Compare 2 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 2 to active level on match
// <2=> Set channel 2 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o26.11> TIM2_CCMR1.OC2PE: Output Compare 2 Preload enabled
// <o26.10> TIM2_CCMR1.OC2FE: Output Compare 2 Fast enabled
// <o26.8..9> TIM2_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <o28.5> TIM2_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: OC2 active high
// <0=> OC2 active high
// <1=> OC2 active low
// <o28.4> TIM2_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: OC2 not active
// <0=> OC2 not active
// <1=> OC2 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o26.12..15> TIM2_CCMR1.IC2F: Input Capture 2 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o26.10..11> TIM2_CCMR1.IC2PSC: Input Capture 2 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o26.8..9> TIM2_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <1=> CC2 configured as input, IC2 mapped on TI2
// <2=> CC2 configured as input, IC2 mapped on TI1
// <3=> CC2 configured as input, IC2 mapped on TRGI
// <o28.5> TIM2_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o28.4> TIM2_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o30> TIM2_CCR2: Capture/compare register 2 <0-65535>
// <i> Set the Compare register value for compare register 2.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 2 channel 3
// <h> Channel 3 Configuration
// <h> Cannel configured as output
// <o27.7> TIM2_CCMR2.OC3CE: Output Compare 3 Clear enabled
// <o27.4..6> TIM2_CCMR2.OC3M: Output Compare 3 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 3 to active level on match
// <2=> Set channel 3 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o27.3> TIM2_CCMR2.OC3PE: Output Compare 3 Preload enabled
// <o27.2> TIM2_CCMR2.OC3FE: Output Compare 3 Fast enabled
// <o27.0..1> TIM2_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <o28.9> TIM2_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: OC3 active high
// <0=> OC3 active high
// <1=> OC3 active low
// <o28.8> TIM2_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: OC3 not active
// <0=> OC3 not active
// <1=> OC3 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o27.4..7> TIM2_CCMR2.IC3F: Input Capture 3 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o27.2..3> TIM2_CCMR2.IC3PSC: Input Capture 3 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o27.0..1> TIM2_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <1=> CC3 configured as input, IC3 mapped on TI3
// <2=> CC3 configured as input, IC3 mapped on TI4
// <3=> CC3 configured as input, IC3 mapped on TRGI
// <o28.9> TIM2_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o28.8> TIM2_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o31> TIM2_CCR3: Capture/compare register 3 <0-65535>
// <i> Set the Compare register value for compare register 3.
// <i> Default: 0
// </h>
//
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