yiweiqicunqi.txt

包内共有六个源代码

library ieee;
use ieee.std_logic_1164.all;
entity yiweijicunqi is
port(clr,lod,clk,s,dir,dil:in bit;
     d:in bit_vector(7 downto 0);
     q:buffer bit_vector(7 downto 0));
end yiweijicunqi;
architecture jiegou of yiweijicunqi is
  signal q_temp:bit_vector(7 downto 0);
   begin
    process(clr,lod,clk,s,dir,dil)
     begin
      if clr='0' then q_temp<="00000000";
        elsif clk'event and clk='1' then
          if(lod='1')then
            q_temp<=d;
            elsif(s='1')then
              for i in 7 downto 1 loop
                q_temp(i-1)<=q(i);
              end loop;
                q_temp(7)<=dir;
             else
              for i in 0 to 6 loop
                q_temp(i+1)<=q(i);
              end loop;
                q_temp(0)<=dil;
          end if;
       end if;
      q<=q_temp;
     end process;
end jiegou;