24jinzhijiajianjishuqi.txt

包内共有六个源代码

library ieee;
use ieee.std_logic_1164.all;
entity count_and_cnt24_18 is
port(s:in std_logic;
     cr:out std_logic;
     co:out std_logic;
     clr:in std_logic;
     clk:in std_logic;
     cnt:buffer integer range 23 downto 0);
end count_and_cnt24_18;
architecture jiegou of count_and_cnt24_18 is
begin
process(s,clr,clk)
  begin
   if s='0' then
     if clr='0' then cnt<=0;
     elsif clk'event and clk='1' then
      if(cnt=23)then
       cnt<=0;
       co<='1';
      else
       cnt<=cnt+1;
       co<='0';
      end if;
     end if;
   else 
       if clr='0' then cnt<=23;
       elsif clk'event and clk='1' then
        if(cnt=0)then
          cnt<=23;
          cr<='1';
        else
          cnt<=cnt-1;
          cr<='0';
        end if;
       end if;
   end if;
  end process;
end jiegou;