top.tan.rpt

来自「FPGA直接读取SD卡扇区数据」· RPT 代码 · 共 189 行 · 第 1/5 页

; fmax Requirement                                                    ; 50 MHz             ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                               ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                              ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; aaa:clk_module|altpll:altpll_component|_clk0 ;                    ; PLL output ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk0     ; 5                     ; 6                   ; -1.833 ns ;              ;
; clk0                                         ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP                 ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'aaa:clk_module|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                    ; To                                                                                                                                                                                ; From Clock                                   ; To Clock                                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.537 ns                                ; None                                                ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndex[2]                                                       ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndexSyncToRdClk[2]                                                                                      ; clk0                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; 2.333 ns                    ; 1.608 ns                  ; 1.071 ns                ;
; 0.541 ns                                ; None                                                ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndex[4]                                                       ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndexSyncToRdClk[4]                                                                                      ; clk0                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; 2.333 ns                    ; 1.608 ns                  ; 1.067 ns                ;
; 0.544 ns                                ; None                                                ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndex[7]                                                       ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndexSyncToRdClk[7]                                                                                      ; clk0                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; 2.333 ns                    ; 1.608 ns                  ; 1.064 ns                ;
; 0.546 ns                                ; None                                                ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndex[1]                                                       ; spiMaster:u_spiMaster|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|bufferInIndexSyncToRdClk[1]                                                                                      ; clk0                                         ; aaa:clk_module|altpll:altpll_component|_clk0 ; 2.333 ns                    ; 1.608 ns                  ; 1.062 ns                ;