top.sta.rpt

FPGA直接读取SD卡扇区数据

+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; top.sdc       ; OK     ; Wed Apr 08 12:36:46 2009 ;
+---------------+--------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                  ;
+--------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------------+------------------------------------------------------------+
; Clock Name                                                               ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                                   ; Targets                                                    ;
+--------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------------+------------------------------------------------------------+
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Generated ; 24.000 ; 41.67 MHz ; 0.000 ; 12.000 ; 50.00      ; 6         ; 5           ;       ;        ;           ;            ; false    ; clk0   ; clk_module|altpll_component|auto_generated|pll1|inclk[0] ; { clk_module|altpll_component|auto_generated|pll1|clk[0] } ;
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[1] ; Generated ; 24.000 ; 41.67 MHz ; 0.000 ; 12.000 ; 50.00      ; 6         ; 5           ;       ;        ;           ;            ; false    ; clk0   ; clk_module|altpll_component|auto_generated|pll1|inclk[0] ; { clk_module|altpll_component|auto_generated|pll1|clk[1] } ;
; clk0                                                                     ; Base      ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                          ; { clk0 }                                                   ;
+--------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                            ;
+-----------+-----------------+--------------------------------------------------------------------------+------+
; Fmax      ; Restricted Fmax ; Clock Name                                                               ; Note ;
+-----------+-----------------+--------------------------------------------------------------------------+------+
; 47.45 MHz ; 47.45 MHz       ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ;      ;
+-----------+-----------------+--------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                              ;
+--------------------------------------------------------------------------+-------+---------------+
; Clock                                                                    ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------+-------+---------------+
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; 2.923 ; 0.000         ;
+--------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                               ;
+--------------------------------------------------------------------------+-------+---------------+
; Clock                                                                    ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------+-------+---------------+
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; 0.422 ; 0.000         ;
+--------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                            ;
+--------------------------------------------------------------------------+--------+---------------+
; Clock                                                                    ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------+--------+---------------+
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; 20.028 ; 0.000         ;
+--------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                            ;
+--------------------------------------------------------------------------+-------+---------------+
; Clock                                                                    ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------+-------+---------------+
; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; 1.382 ; 0.000         ;
+--------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+-------+-----------------+--------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; CCPP  ; Type            ; Clock                                                                    ; Clock Edge ; Target                                                                                                         ;
+--------+--------------+----------------+-------+-----------------+--------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[0]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[10]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[11]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[12]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[13]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[14]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[15]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[16]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[17]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[1]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[2]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[3]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[4]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[5]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[6]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[7]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[8]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_a[9]               ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[18]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[19]              ;
; 11.552 ; 11.434       ; 0.401          ; 0.519 ; Low Pulse Width ; aaa:clk_module|altpll:altpll_component|altpll_l4a1:auto_generated|clk[0] ; Rise       ; or1200_top:or1200_top|or1200_cpu:or1200_cpu|or1200_operandmuxes:or1200_operandmuxes|operand_b[20]              ;