top.sta.rpt

FPGA直接读取SD卡扇区数据

TimeQuest Timing Analyzer report for top
Wed Apr 08 12:37:25 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. SDC File List
  4. Clocks
  5. Slow 1200mV 85C Model Fmax Summary
  6. Slow 1200mV 85C Model Setup Summary
  7. Slow 1200mV 85C Model Hold Summary
  8. Slow 1200mV 85C Model Recovery Summary
  9. Slow 1200mV 85C Model Removal Summary
 10. Slow 1200mV 85C Model Minimum Pulse Width
 11. Setup Times
 12. Hold Times
 13. Clock to Output Times
 14. Minimum Clock to Output Times
 15. Slow 1200mV 0C Model Fmax Summary
 16. Slow 1200mV 0C Model Setup Summary
 17. Slow 1200mV 0C Model Hold Summary
 18. Slow 1200mV 0C Model Recovery Summary
 19. Slow 1200mV 0C Model Removal Summary
 20. Slow 1200mV 0C Model Minimum Pulse Width
 21. Setup Times
 22. Hold Times
 23. Clock to Output Times
 24. Minimum Clock to Output Times
 25. Fast 1200mV 0C Model Setup Summary
 26. Fast 1200mV 0C Model Hold Summary
 27. Fast 1200mV 0C Model Recovery Summary
 28. Fast 1200mV 0C Model Removal Summary
 29. Fast 1200mV 0C Model Minimum Pulse Width
 30. Setup Times
 31. Hold Times
 32. Clock to Output Times
 33. Minimum Clock to Output Times
 34. Multicorner Timing Analysis Summary
 35. Board Trace Model Assignments
 36. Slow Corner Signal Integrity Metrics
 37. Fast Corner Signal Integrity Metrics
 38. Setup Transfers
 39. Hold Transfers
 40. Recovery Transfers
 41. Removal Transfers
 42. Report TCCS
 43. Report RSKM
 44. Unconstrained Paths
 45. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version ;
; Revision Name      ; top                                                             ;
; Device Family      ; Cyclone III                                                     ;
; Device Name        ; EP3C16Q240C8                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Enabled                                                         ;
+--------------------+-----------------------------------------------------------------+


+---------------------------------------------------+
; SDC File List                                     ;