clock.v

来自「FPGA直接读取SD卡扇区数据」· Verilog 代码 · 共 79 行

//
//	The clock for internal clock and sdram clock with two PLL
// 

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on   
`include "define.v"

module clock(clk0,pll0,sdram_clk);	
	
//
// I/O
//		 	 
	input clk0;		
	output pll0; 
	output sdram_clk; 
	
	wire clk0;
	wire pll0;
	wire sdram_clk;
	
//
//	System Clock PLL
//
	
// synopsys translate_off
`library("altpll_component1","ovi_lpm")
// synopsys translate_on 

altpll	altpll_component1 (
				.inclk (clk0),
				.clk (pll0),
				.extclk (sdram_clk)
				// synopsys translate_off
				,
				.activeclock (),
				.areset (),
				.clkbad (),
				.clkena (),
				.clkloss (),
				.clkswitch (),
				.enable0 (),
				.enable1 (),
				.extclkena (),
				.fbin (),
				.locked (),
				.pfdena (),
				.pllena (),
				.scanaclr (),
				.scanclk (),
				.scandata (),
				.scandataout (),
				.scandone (),
				.scanread (),
				.scanwrite (),
				.sclkout0 (),
				.sclkout1 ()
				// synopsys translate_on
				);
	defparam
		altpll_component1.clk0_duty_cycle = 50,
		altpll_component1.lpm_type = "altpll",
		altpll_component1.clk0_multiply_by = 1,
		altpll_component1.inclk0_input_frequency = 25000,
		altpll_component1.extclk0_duty_cycle = 50,
		altpll_component1.clk0_divide_by = `CLK_DIV,
		altpll_component1.extclk0_phase_shift = "0",
		altpll_component1.extclk0_divide_by = `CLK_DIV,
		altpll_component1.pll_type = "AUTO",
		altpll_component1.intended_device_family = "Cyclone",
		altpll_component1.operation_mode = "NORMAL",
		altpll_component1.extclk0_multiply_by = 1,
		altpll_component1.compensate_clock = "CLK0",
		altpll_component1.clk0_phase_shift = "0";


	
endmodule