top.qsf

FPGA直接读取SD卡扇区数据

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144

set_global_assignment -name LAST_QUARTUS_VERSION "8.0 SP1"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME OFF
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED


set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE src/sd_RTL/timescale.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/ctrlStsRegBI.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/initSD.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/readWriteSDBlock.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/readWriteSPIWireData.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sendCmd.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_dpMem_dc.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_fifoRTL.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_RxFifo.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_RxFifoBI.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_TxFifo.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/sm_TxFifoBI.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/spiCtrl.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/spiMaster.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/spiMaster_defines.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/spiMasterWishBoneBI.v
set_global_assignment -name VERILOG_FILE src/sd_RTL/spiTxRxData.v
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE define.v
set_global_assignment -name VERILOG_FILE src/wishbone/tc_top.v
set_global_assignment -name VERILOG_FILE src/wishbone/tc_define.v
set_global_assignment -name VERILOG_FILE src/wishbone/tc_mi_to_st.v
set_global_assignment -name VERILOG_FILE src/wishbone/tc_si_to_mt.v
set_global_assignment -name VERILOG_FILE src/cyclone/clock.v
set_global_assignment -name QIP_FILE aaa.qip
set_global_assignment -name VERILOG_FILE ctrl.v
set_location_assignment PIN_144 -to rstn
set_location_assignment PIN_139 -to sdram_data[3]
set_location_assignment PIN_50 -to sdram_addx[3]
set_location_assignment PIN_49 -to sdram_addx[2]
set_location_assignment PIN_48 -to sdram_addx[1]
set_location_assignment PIN_47 -to sdram_addx[0]
set_location_assignment PIN_42 -to sdram_addx[10]
set_location_assignment PIN_41 -to sdram_ba[1]
set_location_assignment PIN_40 -to sdram_ba[0]
set_location_assignment PIN_39 -to sdram_cs_l
set_location_assignment PIN_38 -to sdram_ras_l
set_location_assignment PIN_37 -to sdram_cas_l
set_location_assignment PIN_143 -to sdram_data[7]
set_location_assignment PIN_142 -to sdram_data[6]
set_location_assignment PIN_141 -to sdram_data[5]
set_location_assignment PIN_140 -to sdram_data[4]
set_location_assignment PIN_134 -to sdram_data[2]
set_location_assignment PIN_133 -to sdram_data[1]
set_location_assignment PIN_132 -to sdram_data[0]
set_location_assignment PIN_36 -to sdram_addx[4]
set_location_assignment PIN_35 -to sdram_addx[5]
set_location_assignment PIN_34 -to sdram_addx[6]
set_location_assignment PIN_33 -to sdram_addx[7]
set_location_assignment PIN_32 -to sdram_addx[8]
set_location_assignment PIN_31 -to sdram_addx[9]
set_location_assignment PIN_28 -to sdram_addx[11]
set_location_assignment PIN_27 -to sdram_cke
set_location_assignment PIN_26 -to sdram_clk
set_location_assignment PIN_11 -to sdram_data[8]
set_location_assignment PIN_10 -to sdram_data[9]
set_location_assignment PIN_7 -to sdram_data[10]
set_location_assignment PIN_6 -to sdram_data[11]
set_location_assignment PIN_5 -to sdram_data[12]
set_location_assignment PIN_4 -to sdram_data[13]
set_location_assignment PIN_3 -to sdram_data[14]
set_location_assignment PIN_2 -to sdram_data[15]
set_location_assignment PIN_1 -to sdram_wr_l

#set_location_assignment PIN_52 -to spi_clk
#set_location_assignment PIN_58 -to spi_cs_n
#set_location_assignment PIN_51 -to spi_miso
#set_location_assignment PIN_57 -to spi_mosi


set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_52 -to sck_o
set_location_assignment PIN_57 -to mosi_o
set_location_assignment PIN_51 -to miso_i
set_location_assignment PIN_58 -to csn_o
set_location_assignment PIN_16 -to clk0
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "ctrl_eth:ctrl_eth|wb_clk_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to "ctrl_eth:ctrl_eth|led" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "ctrl_eth:ctrl_eth|cnt[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "ctrl_eth:ctrl_eth|cnt[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "ctrl_eth:ctrl_eth|cnt[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "ctrl_eth:ctrl_eth|cnt[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "ctrl_eth:ctrl_eth|cnt[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "ctrl_eth:ctrl_eth|cnt[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "ctrl_eth:ctrl_eth|cnt[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "ctrl_eth:ctrl_eth|cnt[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "ctrl_eth:ctrl_eth|cnt[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "ctrl_eth:ctrl_eth|cnt[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "ctrl_eth:ctrl_eth|cnt[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "ctrl_eth:ctrl_eth|cnt[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "ctrl_eth:ctrl_eth|cnt[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "ctrl_eth:ctrl_eth|cnt[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "ctrl_eth:ctrl_eth|cnt[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "ctrl_eth:ctrl_eth|cnt[7]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "ctrl_eth:ctrl_eth|cnt[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "ctrl_eth:ctrl_eth|init_sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "ctrl_eth:ctrl_eth|rw_dat[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "ctrl_eth:ctrl_eth|rw_dat[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "ctrl_eth:ctrl_eth|rw_dat[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "ctrl_eth:ctrl_eth|rw_dat[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "ctrl_eth:ctrl_eth|rw_dat[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "ctrl_eth:ctrl_eth|rw_dat[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "ctrl_eth:ctrl_eth|rw_dat[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "ctrl_eth:ctrl_eth|rw_dat[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "ctrl_eth:ctrl_eth|cnt[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "ctrl_eth:ctrl_eth|init_sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "ctrl_eth:ctrl_eth|rw_dat[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "ctrl_eth:ctrl_eth|rw_dat[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "ctrl_eth:ctrl_eth|rw_dat[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "ctrl_eth:ctrl_eth|rw_dat[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "ctrl_eth:ctrl_eth|rw_dat[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "ctrl_eth:ctrl_eth|rw_dat[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "ctrl_eth:ctrl_eth|rw_dat[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "ctrl_eth:ctrl_eth|rw_dat[7]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=18" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=18" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=79" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=30327" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=26243" -section_id auto_signaltap_0