top.sdc

FPGA直接读取SD卡扇区数据

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# Generated by : Version 6.1 Build 201 11/27/2006 SJ Full Version
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# Project      : top
# Revision     : top
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# Date         : Sun Dec 23 12:04:19 中国标准时间 2007
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# WARNING: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'
#          In SDC, all clocks are related by default
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
# WARNING: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'
#          In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer
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# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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# Original Clock Setting Name: clk0
create_clock -period "50.0 MHz" \
             -name {clk0} {clk0}
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post_message -type warning "Clock -name {tck_pad_i} {tck_pad_i} has no period requirement - check original QSF settings"
post_message -type warning "Clock -name {eth_tx_clk_i} {eth_tx_clk_i} has no period requirement - check original QSF settings"
post_message -type warning "Clock -name {eth_rx_clk_i} {eth_rx_clk_i} has no period requirement - check original QSF settings"
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# Entity Specific Timing Assignments found in
# the Timing Analyzer Settings report panel
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