usb_regs.h

基于ＳＴ ＡＲＭ处理器的ＵＳＢ通信的演示

/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name          : usb_regs.h
* Author             : MCD Application Team
* Date First Issued  : 10/27/2003 : V1.0
* Description        : Interface prototype functions to USB cell registers
********************************************************************************
* History:
* 09/18/2006 : V3.0
* 09/01/2006 : V2.0
* 10/27/2003 : V1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#define STR7xx  /*STR7 family*/
#define STR71x  /* STR71x */
#ifndef __USB_REGS_H
#define __USB_REGS_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/

typedef enum _EP_DBUF_DIR{		/* double buffered endpoint direction */
 EP_DBUF_ERR,
 EP_DBUF_OUT,
 EP_DBUF_IN
}EP_DBUF_DIR;

/* endpoint buffer number */
enum EP_BUF_NUM{ 
 EP_NOBUF, 
 EP_BUF0, 
 EP_BUF1
};

/* Exported constants --------------------------------------------------------*/
#ifdef STR7xx

  #ifdef STR71x /*STR71x family*/
  #define RegBase  (0xC0008800L)  /* USB_IP Peripheral Registers base address */
  #define PMAAddr  (0xC0008000L)  /* USB_IP Packet Memory Area base address   */
  #endif /*end of STR71x family*/
  
  #ifdef STR75x /*STR75x family*/
  #define RegBase  (0xFFFFA800L)  /* USB_IP Peripheral Registers base address */
  #define PMAAddr  (0xFFFFA000L)  /* USB_IP Packet Memory Area base address   */
  #endif /*end of STR75x family*/
 
#endif /*end of STR7xx family*/

#ifdef STR91x /*STR91x family*/

  #ifdef STR91x_USB_BUFFERED
  #define RegBase  (0x60000800L)  /* USB_IP Peripheral Registers base address */
  #define PMAAddr  (0x60000000L)  /* USB_IP Packet Memory Area base address */
  #endif
  
  #ifdef STR91x_USB_NON_BUFFERED
  #define RegBase  (0x70000800L)  /* USB_IP Peripheral Registers base address */
  #define PMAAddr  (0x70000000L)  /* USB_IP Packet Memory Area base address */
  #endif
#endif

/* General registers */
#define CNTR    ((volatile unsigned *)(RegBase + 0x40))	/* Control register           */
#define ISTR    ((volatile unsigned *)(RegBase + 0x44))	/* Interrupt status register  */
#define FNR     ((volatile unsigned *)(RegBase + 0x48)) /* Frame number register      */
#define DADDR   ((volatile unsigned *)(RegBase + 0x4C))	/* Device address register    */
#define BTABLE  ((volatile unsigned *)(RegBase + 0x50))	/* Buffer Table address register */

#ifdef STR91x /*STR91x family DMA registers*/

#define DMACR1  ((volatile unsigned *)(RegBase + 0x54)) /* DMA control register 1 */
#define DMACR2  ((volatile unsigned *)(RegBase + 0x58)) /* DMA control register 2 */
#define DMACR3  ((volatile unsigned *)(RegBase + 0x5C)) /* DMA control register 3 */
#define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))/* DMA burst size register */
#define DMALLI  ((volatile unsigned *)(RegBase + 0x64)) /* DMA LLI register */

#endif

/* Endpoint registers */
#define EP0REG  ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */
/* endpoints enumeration */
#define ENDP0	 ((u8)0)
#define ENDP1	 ((u8)1)
#define ENDP2	 ((u8)2)
#define ENDP3	 ((u8)3)
#define ENDP4	 ((u8)4)
#define ENDP5	 ((u8)5)
#define ENDP6	 ((u8)6)
#define ENDP7	 ((u8)7)  /* Only 8  endpoints for STR75x Family */
#define ENDP8	 ((u8)8)
#define ENDP9	 ((u8)9)  /* Only 10 endpoints for STR91x Family */
#define ENDP10	 ((u8)10)
#define ENDP11	 ((u8)11)
#define ENDP12	 ((u8)12)
#define ENDP13	 ((u8)13)
#define ENDP14	 ((u8)14)
#define ENDP15	 ((u8)15)

/*******************************************************************************/
/* 							ISTR interrupt events  							   */
/*******************************************************************************/
#define ISTR_CTR   	(0x8000)	/* Correct TRansfer	        (clear-only bit) */
#define ISTR_DOVR  	(0x4000)	/* DMA OVeR/underrun		(clear-only bit) */
#define ISTR_ERR   	(0x2000)	/* ERRor			(clear-only bit) */
#define ISTR_WKUP  	(0x1000)	/* WaKe UP			(clear-only bit) */
#define ISTR_SUSP  	(0x0800)	/* SUSPend			(clear-only bit) */
#define ISTR_RESET 	(0x0400)	/* RESET			(clear-only bit) */
#define ISTR_SOF   	(0x0200)	/* Start Of Frame		(clear-only bit) */
#define ISTR_ESOF  	(0x0100)	/* Expected Start Of Frame	(clear-only bit) */

#ifdef STR91x /*STR91x family*/
#define ISTR_SZDPR      (0x0080)  /* Short or Zero-Length Received Data Packet */
#endif 

#define ISTR_DIR   	(0x0010)	 /* DIRection of transaction	(read-only bit)  */
#define ISTR_EP_ID 	(0x000F)	 /* EndPoint IDentifier		(read-only bit)  */

#define CLR_CTR   	(~ISTR_CTR)	 /* clear Correct TRansfer bit */
#define CLR_DOVR  	(~ISTR_DOVR)     /* clear DMA OVeR/underrun	bit*/
#define CLR_ERR   	(~ISTR_ERR)	 /* clear ERRor	bit */
#define CLR_WKUP  	(~ISTR_WKUP)     /* clear WaKe UP bit		   */
#define CLR_SUSP  	(~ISTR_SUSP)     /* clear SUSPend bit		   */
#define CLR_RESET 	(~ISTR_RESET)    /* clear RESET	bit			   */
#define CLR_SOF   	(~ISTR_SOF)	 /* clear Start Of Frame bit   */
#define CLR_ESOF  	(~ISTR_ESOF) /* clear Expected Start Of Frame bit */

#ifdef STR91x /*STR91x family*/
#define CLR_SZDPR   (~ISTR_SZDPR)/* clear SZDPR bit */
#endif 

/*******************************************************************************/
/*				 CNTR control register bits definitions						   */
/*******************************************************************************/
#define CNTR_CTRM   (0x8000)	/* Correct TRansfer Mask */
#define CNTR_DOVRM  (0x4000)	/* DMA OVeR/underrun Mask */
#define CNTR_ERRM   (0x2000)	/* ERRor Mask */
#define CNTR_WKUPM  (0x1000)	/* WaKe UP Mask */
#define CNTR_SUSPM  (0x0800)	/* SUSPend Mask	*/
#define CNTR_RESETM (0x0400)	/* RESET Mask   */
#define CNTR_SOFM   (0x0200)	/* Start Of Frame Mask */
#define CNTR_ESOFM  (0x0100)	/* Expected Start Of Frame Mask */

#ifdef STR91x /*STR91x family*/
#define CNTR_SZDPRM (0x0080)    /* Short or Zero-Length Received Data Packet Mask*/
#endif

#define CNTR_RESUME (0x0010)	/* RESUME request */
#define CNTR_FSUSP  (0x0008)	/* Force SUSPend */
#define CNTR_LPMODE (0x0004)	/* Low-power MODE	*/
#define CNTR_PDWN   (0x0002)	/* Power DoWN */
#define CNTR_FRES   (0x0001)	/* Force USB RESet */

/*******************************************************************************/
/* 					FNR Frame Number Register bit definitions				   */
/*******************************************************************************/
#define FNR_RXDP	(0x8000)	/* status of D+ data line */
#define FNR_RXDM	(0x4000)	/* status of D- data line */
#define FNR_LCK		(0x2000)	/* LoCKed */
#define FNR_LSOF	(0x1800)	/* Lost SOF */
#define FNR_FN		(0x07FF)	/* Frame Number */
/*******************************************************************************/
/*					DADDR Device ADDRess bit definitions					   */
/*******************************************************************************/
#define DADDR_EF	(0x80)
#define DADDR_ADD	(0x7F)
/*===============================================================================*/
/* Endpoint register */
/*===============================================================================*/
/* bit positions */
#define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX 	*/
#define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */
#define EPRX_STAT      (0x3000)	/* EndPoint RX STATus bit field */
#define EP_SETUP       (0x0800)	/* EndPoint SETUP */
#define EP_T_FIELD     (0x0600) /* EndPoint TYPE */
#define EP_KIND        (0x0100) /* EndPoint KIND */
#define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */
#define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */
#define EPTX_STAT      (0x0030)	/* EndPoint TX STATus bit field */
#define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */

/* EndPoint REGister MASK (no toggle fields) */
#define EPREG_MASK     (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)

/* EP_TYPE[1:0] EndPoint TYPE */
#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
#define EP_BULK        (0x0000)	/* EndPoint BULK */
#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)


/* EP_KIND EndPoint KIND */
#define EPKIND_MASK    (~EP_KIND & EPREG_MASK)

/* STAT_TX[1:0] STATus for TX transfer */
#define EP_TX_DIS      (0x0000)	/* EndPoint TX DISabled */
#define EP_TX_STALL    (0x0010)	/* EndPoint TX STALLed */
#define EP_TX_NAK      (0x0020) /* EndPoint TX NAKed */
#define EP_TX_VALID    (0x0030)	/* EndPoint TX VALID */
#define EPTX_DTOG1     (0x0010)	/* EndPoint TX Data TOGgle bit1 */
#define EPTX_DTOG2     (0x0020)	/* EndPoint TX Data TOGgle bit2 */
#define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)

/* STAT_RX[1:0] STATus for RX transfer */
#define EP_RX_DIS      (0x0000)	/* EndPoint RX DISabled */
#define EP_RX_STALL    (0x1000)	/* EndPoint RX STALLed */
#define EP_RX_NAK      (0x2000)	/* EndPoint RX NAKed */
#define EP_RX_VALID    (0x3000)	/* EndPoint RX VALID */
#define EPRX_DTOG1     (0x1000)	/* EndPoint RX Data TOGgle bit1 */
#define EPRX_DTOG2     (0x2000)	/* EndPoint RX Data TOGgle bit1 */
#define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)

/* Exported macro ------------------------------------------------------------*/
/*----------------------------------------------------------------*/
/* SetCNTR */
/*----------------------------------------------------------------*/
#define _SetCNTR(wRegValue)	 (*CNTR   = (u16)wRegValue)
/*----------------------------------------------------------------*/
/* SetISTR */
/*----------------------------------------------------------------*/
#define _SetISTR(wRegValue)	 (*ISTR   = (u16)wRegValue)
/*----------------------------------------------------------------*/
/* SetDADDR */
/*----------------------------------------------------------------*/
#define _SetDADDR(wRegValue) (*DADDR  = (u16)wRegValue)
/*----------------------------------------------------------------*/
/* SetBTABLE */
/*----------------------------------------------------------------*/
#define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8))
/*----------------------------------------------------------------*/
/* GetCNTR */
/*----------------------------------------------------------------*/
#define _GetCNTR()   ((u16) *CNTR)
/*----------------------------------------------------------------*/
/* GetISTR */
/*----------------------------------------------------------------*/