bf561_micron_image_capture_mt9v022_mt9v032.ldf

adi black fin chip connect to cmos sensor

         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-A>  */
         
      } > MEM_A_L1_SCRATCH

      L1_code
      {
         INPUT_SECTION_ALIGN(4)
         __CORE = 0;
         INPUT_SECTIONS($OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(program))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code>   */
         
      } > MEM_A_L1_CODE

      L1_data_a
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_data_cache_a = 0;
         INPUT_SECTIONS($OBJECTS_CORE_A(L1_data_a) $LIBRARIES_CORE_A(L1_data_a))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_a>  */
         
         RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 2K,4)
         INPUT_SECTIONS($OBJECTS_CORE_A{DualCoreMem("CoreA")}(cplb_data) $LIBRARIES_CORE_A{DualCoreMem("CoreA")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(data1))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_a>  */
         
      } > MEM_A_L1_DATA_A

      bsz_L1_data_a ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
      } > MEM_A_L1_DATA_A

      L1_data_a_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
         RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
         ldf_heap_space = heaps_and_stack_in_L1_data_a;
         ldf_heap_end = (ldf_heap_space + (((heaps_and_stack_in_L1_data_a_length * 2K) / 2K) - 4)) & 0xfffffffc;
         ldf_heap_length = ldf_heap_end - ldf_heap_space;
      } > MEM_A_L1_DATA_A

      L1_data_b
      {
         INPUT_SECTION_ALIGN(4)
         FORCE_CONTIGUITY
         ___l1_data_cache_b = 0;
         INPUT_SECTIONS($OBJECTS_CORE_A(L1_data_b) $LIBRARIES_CORE_A(L1_data_b))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_b>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_b>  */
         
         RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 2K,4)
         INPUT_SECTIONS($OBJECTS_CORE_A(ctor) $LIBRARIES_CORE_A(ctor))
         INPUT_SECTIONS($OBJECTS_CORE_A(ctorl) $LIBRARIES_CORE_A(ctorl))
         INPUT_SECTIONS($OBJECTS_CORE_A(vtbl) $LIBRARIES_CORE_A(vtbl))
         INPUT_SECTIONS($OBJECTS_CORE_A(.gdt) $LIBRARIES_CORE_A(.gdt))
         INPUT_SECTIONS($OBJECTS_CORE_A(.gdtl) $LIBRARIES_CORE_A(.gdtl))
         INPUT_SECTIONS($OBJECTS_CORE_A(.frt) $LIBRARIES_CORE_A(.frt))
         INPUT_SECTIONS($OBJECTS_CORE_A(.rtti) $LIBRARIES_CORE_A(.rtti))
         INPUT_SECTIONS($OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(data1))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A{DualCoreMem("CoreA")}(cplb_data) $LIBRARIES_CORE_A{DualCoreMem("CoreA")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_b>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_b>  */
         
      } > MEM_A_L1_DATA_B

      bsz_L1_data_b ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(bsz))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(bsz))
         INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
      } > MEM_A_L1_DATA_B

      L1_data_b_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
         RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4)
         ldf_stack_space = heaps_and_stack_in_L1_data_b;
         ldf_stack_end = (ldf_stack_space + (((heaps_and_stack_in_L1_data_b_length * 2K) / 2K) - 4)) & 0xfffffffc;
      } > MEM_A_L1_DATA_B

      L2_sram_a
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(L2_sram) $LIBRARIES_CORE_A(L2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_A(l2_sram) $LIBRARIES_CORE_A(l2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-L2_sram_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L2_sram_a>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_A{DualCoreMem("CoreA")}(cplb_data) $LIBRARIES_CORE_A{DualCoreMem("CoreA")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))
         INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L2_sram_a>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L2_sram_a>  */
         
      } > MEM_L2_SRAM_A

      bsz_L2_sram_a ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
      } > MEM_L2_SRAM_A

      L2_sram_a_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
      } > MEM_L2_SRAM_A

      L2_shared
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($LIBRARIES_SHARED{sharing("MustShare")}(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(L2_sram) $LIBRARIES_SHARED(L2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_A(l2_sram) $LIBRARIES_SHARED(l2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_A(l2_shared) $LIBRARIES_SHARED(l2_shared))
         INPUT_SECTIONS($OBJECTS_CORE_A(primio_atomic_lock) $LIBRARIES_SHARED(primio_atomic_lock))
      } > MEM_L2_SRAM

      sdram_bank0_1
      {
         INPUT_SECTION_ALIGN(4)
         /* Place shared program code in the section sdram_shared.
         * and use the LDF RESOLVE command from Core B.
         */
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_shared) $LIBRARIES_CORE_A(sdram_shared))
         
         /*$VDSG<insert-input-sections-at-shared-sdram>         */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-shared-sdram>         */
         
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data_bank0) $LIBRARIES_CORE_A(sdram_data_bank0))
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank0) $LIBRARIES_CORE_A(sdram_bank0))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank0_1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank0_1>  */
         
      } > MEM_SDRAM_BANK0

      sdram_bank1_1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data_bank1) $LIBRARIES_CORE_A(sdram_data_bank1))
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank1) $LIBRARIES_CORE_A(sdram_bank1))
         INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1_1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1_1>  */
         
      } > MEM_SDRAM_BANK1

      sdram_bank2_1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank2) $LIBRARIES_CORE_A(sdram_bank2))
         INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))
         INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2>  */
         
      } > MEM_SDRAM_BANK2

      sdram_bank2_2
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data_bank2) $LIBRARIES_CORE_A(sdram_data_bank2))
         INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2_2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2_2>  */
         
      } > MEM_SDRAM_BANK2

      sdram_bank2_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bsz) $LIBRARIES_CORE_A(sdram_bsz))
         INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))
      } > MEM_SDRAM_BANK2

      sdram_bank2_3
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank2) $LIBRARIES_CORE_A(sdram_bank2))
         INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2_3>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2_3>  */
         
      } > MEM_SDRAM_BANK2

      sdram_bank3_1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_data_bank3) $LIBRARIES_CORE_A(sdram_data_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank3) $LIBRARIES_CORE_A(sdram_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
         INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_1>  */
         
      } > MEM_SDRAM_BANK3

      
      /*$VDSG<insert-new-sections-at-the-end-for-CORE-A>        */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-end-for-CORE-A>        */
      
   } /* SECTIONS */
} /* p0 */