cpux_05.c

Extended Memory Access Using IAR v3.42A and CCE v2

//******************************************************************************
//   MSP430xG461x Demo - ADC12, DMA0, Repeatedly Sample A0 until Extended Flash 
//                      memory range is completely filled, TB1 as sample trigger 
//
// This program demonstrates how ADC12 conversion results are written directly 
// to the extended flash via the DMA. 
//
// Description: ADC12, Channel A0 is sampled at the rate of ~8000 samples/sec  
// (most suitable for voice recording). Timer B is used in up mode, TBCCR1 sets  
// the PWM duty cycle. Rising edge of Timer_BOUT1 triggers the sample and hold 
// process in ADC12. Conversion result is loaded in ADCMEM0 and this triggers
// the DMA0 to transfer the conversion  result to the extended flash. This is
// repeated until the extended memory is completely filled. DMA0SZ = 0, DMAIFG 
// is set and CPU exits LPM0 mode and disables all MSP430 modules and goes to 
// LPM4 mode. 
//	Before writing into the extended flash, all the extended memory contents
// are erased. LED2 is on during extended flash erase. LED4 is turned on
// when ADC12 conversion begins and is turned off when extended flash range is
// completely filled indicating recording is over.
// ACLK = 32kHz, MCLK = SMCLK = default DCO 1048576Hz, ADC12CLK = ADC12OSC
//
//                MSP430xG461x
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz
//          --|RST          XOUT|-
//            |                 |
//            |             P2.1|--> LED2 
//     Vin -->|P6.0/A0      P5.1|--> LED4
//
//   Bhargavi Nisarga
//   Texas Instruments Inc.
//   June 2007
//   Built with IAR Embedded Workbench Version: 3.42A
//******************************************************************************

#include "msp430xG46x.h"
#include "intrinsics.h"

#define MEMSTART_HIGH   0x10000             // Ext memory range(device specific)
#define MEMEND_HIGH     0x1FFFF

void Record(void);
void Erase_Flash(void);

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
  P2DIR |= BIT1;                            // Set P2.1 to o/p direction [LED2]
  P2OUT = 0x00;
  P5DIR |= BIT1;                            // Set P5.1 to o/p direction [LED4]
  P5OUT = 0x00;
  Record();
  __bis_SR_register(LPM4_bits + GIE);       // Enable interrupts, enter LPM4  
}

void Record(void)
{
  volatile unsigned int i;
  // Configure ADC12 module  
  ADC12MCTL0 = SREF_1 + INCH_0;             // Channel A0, Vref+
  ADC12IFG = 0;
  ADC12CTL1 = SHS_3 + CONSEQ_2;             // S&H TB.OUT1, rep. single channel
  ADC12CTL0 = REF2_5V + REFON + ADC12ON;    // VRef ADC12 on, enabled

  for (i = 0x3600; i; i--);                 // Delay for needed ref start-up.
                                            // See datasheet for details.
  ADC12CTL0 |= ENC;                         // Enable conversions

  // Configure Timer B to sample ADC12 channel A0~8500 Sa/sec (SMCLK prd * 110)
  TBCCR0 = 110;                             // Init TBCCR0 w/ sample prd
  TBCCR1 = 80;                              // Trigger for ADC12 SC
  TBCCTL1 = OUTMOD_7;                       // Reset OUT1 on EQU1, set on EQU0  

  // Configure DMA0 
  DMACTL0 = DMA0TSEL_6;                     // ADC12IFGx triggers DMA0 
  DMA0SA = (unsigned int)&ADC12MEM0;        // Src address = ADC12 module
  __data16_write_addr((unsigned short)&DMA0DA, MEMSTART_HIGH); 
                                            // use intrinsic to access 20-bit 
                                            // SFRs in the lower 64 KB.
  DMA0SZ = (MEMEND_HIGH - MEMSTART_HIGH) >> 1;  // Size (DMA word transfer)  
  DMA0CTL = DMADSTINCR_3 + DMAIE + DMAEN;   // Destn incr, DMA interrupt enable
   
  // Configue Flash memory
  FCTL2 = FWKEY + FSSEL1 + FN1;             // Fftg = SMCLK/(FNx + 1)  
  FCTL3 = FWKEY;                            // Unlock Flash memory for write
  Erase_Flash();                            // Call Flash erase function
  FCTL1 = FWKEY + WRT;                      // Enable Flash write for recording

  P5OUT |= BIT1;                            // Set P5.1 (LED4 on)
  TBCTL = TBSSEL_2 + MC_1 + TBCLR;          // SMCLK, clear TBR, up mode 
  
  // Activate LPM during DMA recording, wake-up when finished
  __bis_SR_register(LPM0_bits + GIE);       // Enable interrupts, enter LPM0
  __disable_interrupt();                    // Disable interrupts
  
  // Deactivate Flash memory write access
  FCTL1 = FWKEY;                            // Disable Flash write
  FCTL3 = FWKEY + LOCK;                     // Lock Flash memory
  
  // Power-down MSP430 modules
  ADC12CTL1 &= ~CONSEQ_2;                   // Stop conversion 
  ADC12CTL0 &= ~ENC;                        // Disable ADC12 conversion
  ADC12CTL0 = 0;                            // Switch off ADC12 & ref voltage
  TBCTL = 0;                                // Disable Timer_B
  P5OUT &= ~BIT1;                           // LED4 off
}

void Erase_Flash(void)
{
  unsigned long pointer_high = MEMSTART_HIGH;
  P2OUT |= BIT1;                            // LED2 on when Flash is erased.
  while(pointer_high < MEMEND_HIGH)         // Chk if ptr is within memory range
  {
    FCTL1 = FWKEY + ERASE;
    __data20_write_char(pointer_high, 0x00);// Intrnsic to write to extnd memory
                                            // Segment erase
    pointer_high += 0x0200;                 // Point to next segment
  }
  P2OUT ^= BIT1;                            // LED2 off when Flash Erase over
}

// DMA0 Interrupt service routine
#pragma vector=DMA_VECTOR
__interrupt void DMA_ISR(void)
{
  DMA0CTL &= ~DMAIFG;                       // Clear DMA0 INT flag
  __bic_SR_register_on_exit(LPM0_bits);     // Exit LPM0 
}