quartus ii -

quartus ii 数字钟设计

; N/A   ; None         ; 7.647 ns   ; 74161:inst3|f74161:sub|9   ; QHH0 ; CLK        ;
; N/A   ; None         ; 7.498 ns   ; 74161:inst2|f74161:sub|87  ; QHL1 ; CLK        ;
; N/A   ; None         ; 6.868 ns   ; 74161:inst2|f74161:sub|99  ; QHL2 ; CLK        ;
; N/A   ; None         ; 6.836 ns   ; 74161:inst|f74161:sub|110  ; QML3 ; CLK        ;
; N/A   ; None         ; 6.822 ns   ; 74161:inst1|f74161:sub|9   ; QMH0 ; CLK        ;
; N/A   ; None         ; 6.575 ns   ; 74161:inst|f74161:sub|87   ; QML1 ; CLK        ;
; N/A   ; None         ; 6.573 ns   ; 74161:inst|f74161:sub|9    ; QML0 ; CLK        ;
; N/A   ; None         ; 6.546 ns   ; 74161:inst|f74161:sub|99   ; QML2 ; CLK        ;
; N/A   ; None         ; 6.417 ns   ; 74161:inst3|f74161:sub|110 ; QHH3 ; CLK        ;
; N/A   ; None         ; 6.381 ns   ; 74161:inst2|f74161:sub|9   ; QHL0 ; CLK        ;
; N/A   ; None         ; 6.257 ns   ; 74161:inst1|f74161:sub|87  ; QMH1 ; CLK        ;
; N/A   ; None         ; 6.248 ns   ; 74161:inst1|f74161:sub|99  ; QMH2 ; CLK        ;
; N/A   ; None         ; 6.238 ns   ; 74161:inst1|f74161:sub|110 ; QMH3 ; CLK        ;
+-------+--------------+------------+----------------------------+------+------------+


+---------------------------------------------------------------------------------------+
; th                                                                                    ;
+---------------+-------------+-----------+------+---------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                        ; To Clock ;
+---------------+-------------+-----------+------+---------------------------+----------+
; N/A           ; None        ; -5.881 ns ; EN   ; 74161:inst|f74161:sub|9   ; CLK      ;
; N/A           ; None        ; -6.395 ns ; EN   ; 74161:inst|f74161:sub|87  ; CLK      ;
; N/A           ; None        ; -6.509 ns ; EN   ; 74161:inst|f74161:sub|99  ; CLK      ;
; N/A           ; None        ; -7.375 ns ; EN   ; 74161:inst|f74161:sub|110 ; CLK      ;
+---------------+-------------+-----------+------+---------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Aug 29 08:48:52 2013
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lbstry -c lbstry --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 155.52 MHz between source register "74161:inst|f74161:sub|110" and destination register "74161:inst2|f74161:sub|99" (period= 6.43 ns)
    Info: + Longest register to register delay is 6.169 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N3; Fanout = 3; REG Node = '74161:inst|f74161:sub|110'
        Info: 2: + IC(0.533 ns) + CELL(0.442 ns) = 0.975 ns; Loc. = LC_X4_Y1_N5; Fanout = 7; COMB Node = 'inst9~70'
        Info: 3: + IC(0.432 ns) + CELL(0.442 ns) = 1.849 ns; Loc. = LC_X4_Y1_N2; Fanout = 6; COMB Node = 'inst15~24'
        Info: 4: + IC(0.447 ns) + CELL(0.292 ns) = 2.588 ns; Loc. = LC_X4_Y1_N9; Fanout = 5; COMB Node = 'inst17~20'
        Info: 5: + IC(0.449 ns) + CELL(0.292 ns) = 3.329 ns; Loc. = LC_X4_Y1_N0; Fanout = 4; COMB Node = 'inst17'
        Info: 6: + IC(1.112 ns) + CELL(0.292 ns) = 4.733 ns; Loc. = LC_X2_Y1_N1; Fanout = 3; COMB Node = '74161:inst2|f74161:sub|77~46'
        Info: 7: + IC(1.127 ns) + CELL(0.309 ns) = 6.169 ns; Loc. = LC_X5_Y1_N7; Fanout = 3; REG Node = '74161:inst2|f74161:sub|99'
        Info: Total cell delay = 2.069 ns ( 33.54 % )
        Info: Total interconnect delay = 4.100 ns ( 66.46 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.612 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(0.426 ns) + CELL(0.711 ns) = 2.612 ns; Loc. = LC_X5_Y1_N7; Fanout = 3; REG Node = '74161:inst2|f74161:sub|99'
            Info: Total cell delay = 2.186 ns ( 83.69 % )
            Info: Total interconnect delay = 0.426 ns ( 16.31 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.612 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(0.426 ns) + CELL(0.711 ns) = 2.612 ns; Loc. = LC_X4_Y1_N3; Fanout = 3; REG Node = '74161:inst|f74161:sub|110'
            Info: Total cell delay = 2.186 ns ( 83.69 % )
            Info: Total interconnect delay = 0.426 ns ( 16.31 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "74161:inst|f74161:sub|110" (data pin = "EN", clock pin = "CLK") is 7.427 ns
    Info: + Longest pin to register delay is 10.002 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'EN'
        Info: 2: + IC(5.005 ns) + CELL(0.442 ns) = 6.922 ns; Loc. = LC_X3_Y1_N6; Fanout = 2; COMB Node = '74161:inst|f74161:sub|80'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 7.218 ns; Loc. = LC_X3_Y1_N7; Fanout = 2; COMB Node = '74161:inst|f74161:sub|84'
        Info: 4: + IC(1.077 ns) + CELL(0.114 ns) = 8.409 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; COMB Node = '74161:inst|f74161:sub|94'
        Info: 5: + IC(1.115 ns) + CELL(0.478 ns) = 10.002 ns; Loc. = LC_X4_Y1_N3; Fanout = 3; REG Node = '74161:inst|f74161:sub|110'
        Info: Total cell delay = 2.623 ns ( 26.22 % )
        Info: Total interconnect delay = 7.379 ns ( 73.78 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.612 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(0.426 ns) + CELL(0.711 ns) = 2.612 ns; Loc. = LC_X4_Y1_N3; Fanout = 3; REG Node = '74161:inst|f74161:sub|110'
        Info: Total cell delay = 2.186 ns ( 83.69 % )
        Info: Total interconnect delay = 0.426 ns ( 16.31 % )
Info: tco from clock "CLK" to destination pin "QHH1" through register "74161:inst3|f74161:sub|87" is 7.935 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.612 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(0.426 ns) + CELL(0.711 ns) = 2.612 ns; Loc. = LC_X5_Y1_N9; Fanout = 5; REG Node = '74161:inst3|f74161:sub|87'
        Info: Total cell delay = 2.186 ns ( 83.69 % )
        Info: Total interconnect delay = 0.426 ns ( 16.31 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.099 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N9; Fanout = 5; REG Node = '74161:inst3|f74161:sub|87'
        Info: 2: + IC(2.975 ns) + CELL(2.124 ns) = 5.099 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'QHH1'
        Info: Total cell delay = 2.124 ns ( 41.66 % )
        Info: Total interconnect delay = 2.975 ns ( 58.34 % )
Info: th for register "74161:inst|f74161:sub|9" (data pin = "EN", clock pin = "CLK") is -5.881 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.612 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(0.426 ns) + CELL(0.711 ns) = 2.612 ns; Loc. = LC_X3_Y1_N9; Fanout = 4; REG Node = '74161:inst|f74161:sub|9'
        Info: Total cell delay = 2.186 ns ( 83.69 % )
        Info: Total interconnect delay = 0.426 ns ( 16.31 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.508 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'EN'
        Info: 2: + IC(5.028 ns) + CELL(0.590 ns) = 7.093 ns; Loc. = LC_X3_Y2_N2; Fanout = 1; COMB Node = '74161:inst|f74161:sub|78'
        Info: 3: + IC(1.106 ns) + CELL(0.309 ns) = 8.508 ns; Loc. = LC_X3_Y1_N9; Fanout = 4; REG Node = '74161:inst|f74161:sub|9'
        Info: Total cell delay = 2.374 ns ( 27.90 % )
        Info: Total interconnect delay = 6.134 ns ( 72.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Aug 29 08:48:52 2013
    Info: Elapsed time: 00:00:00