quartus ii -

quartus ii 数字钟设计

Timing Analyzer report for lbstry
Thu Aug 29 08:48:52 2013
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                ;
+------------------------------+-------+---------------+----------------------------------+---------------------------+---------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                      ; To                        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------------------+---------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.427 ns                         ; EN                        ; 74161:inst|f74161:sub|110 ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.935 ns                         ; 74161:inst3|f74161:sub|87 ; QHH1                      ; CLK        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -5.881 ns                        ; EN                        ; 74161:inst|f74161:sub|9   ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 155.52 MHz ( period = 6.430 ns ) ; 74161:inst|f74161:sub|110 ; 74161:inst2|f74161:sub|99 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                           ;                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------+---------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                           ;
+-------+------------------------------------------------+----------------------------+----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                       ; To                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------+----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 155.52 MHz ( period = 6.430 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst2|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 6.169 ns                ;
; N/A   ; 157.23 MHz ( period = 6.360 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst2|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 6.099 ns                ;
; N/A   ; 163.75 MHz ( period = 6.107 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst3|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 5.846 ns                ;
; N/A   ; 165.21 MHz ( period = 6.053 ns )               ; 74161:inst1|f74161:sub|9   ; 74161:inst2|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.792 ns                ;
; N/A   ; 165.65 MHz ( period = 6.037 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst3|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 5.776 ns                ;
; N/A   ; 166.22 MHz ( period = 6.016 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst3|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.755 ns                ;
; N/A   ; 168.18 MHz ( period = 5.946 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst3|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.685 ns                ;
; N/A   ; 168.29 MHz ( period = 5.942 ns )               ; 74161:inst1|f74161:sub|99  ; 74161:inst2|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.681 ns                ;
; N/A   ; 174.40 MHz ( period = 5.734 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst3|f74161:sub|9   ; CLK        ; CLK      ; None                        ; None                      ; 5.473 ns                ;
; N/A   ; 174.52 MHz ( period = 5.730 ns )               ; 74161:inst1|f74161:sub|9   ; 74161:inst3|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 5.469 ns                ;
; N/A   ; 174.58 MHz ( period = 5.728 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst2|f74161:sub|9   ; CLK        ; CLK      ; None                        ; None                      ; 5.467 ns                ;
; N/A   ; 175.99 MHz ( period = 5.682 ns )               ; 74161:inst|f74161:sub|110  ; 74161:inst3|f74161:sub|87  ; CLK        ; CLK      ; None                        ; None                      ; 5.421 ns                ;
; N/A   ; 176.55 MHz ( period = 5.664 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst3|f74161:sub|9   ; CLK        ; CLK      ; None                        ; None                      ; 5.403 ns                ;
; N/A   ; 176.74 MHz ( period = 5.658 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst2|f74161:sub|9   ; CLK        ; CLK      ; None                        ; None                      ; 5.397 ns                ;
; N/A   ; 177.34 MHz ( period = 5.639 ns )               ; 74161:inst1|f74161:sub|9   ; 74161:inst3|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.378 ns                ;
; N/A   ; 177.97 MHz ( period = 5.619 ns )               ; 74161:inst1|f74161:sub|99  ; 74161:inst3|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 5.358 ns                ;
; N/A   ; 178.19 MHz ( period = 5.612 ns )               ; 74161:inst|f74161:sub|9    ; 74161:inst3|f74161:sub|87  ; CLK        ; CLK      ; None                        ; None                      ; 5.351 ns                ;
; N/A   ; 178.41 MHz ( period = 5.605 ns )               ; 74161:inst2|f74161:sub|9   ; 74161:inst2|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.344 ns                ;
; N/A   ; 180.90 MHz ( period = 5.528 ns )               ; 74161:inst1|f74161:sub|99  ; 74161:inst3|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 5.267 ns                ;