📄 quartus ii -
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; 74161:inst1|f74161:sub|90~3 ; 1 ;
; 74161:inst1|f74161:sub|78~3 ; 1 ;
; 74161:inst|f74161:sub|97 ; 1 ;
; 74161:inst|f74161:sub|90 ; 1 ;
; 74161:inst|f74161:sub|78 ; 1 ;
; 74161:inst3|f74161:sub|94 ; 1 ;
; 74161:inst2|f74161:sub|94 ; 1 ;
; 74161:inst1|f74161:sub|94 ; 1 ;
; 74161:inst|f74161:sub|94 ; 1 ;
+------------------------------+---------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 29 / 8,840 ( < 1 % ) ;
; Direct links ; 14 / 11,506 ( < 1 % ) ;
; Global clocks ; 1 / 8 ( 12 % ) ;
; LAB clocks ; 1 / 156 ( < 1 % ) ;
; LUT chains ; 7 / 2,619 ( < 1 % ) ;
; Local interconnects ; 51 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 26 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.67) ; Number of LABs (Total = 6) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 4 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 0.83) ; Number of LABs (Total = 6) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 5 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 7.67) ; Number of LABs (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 4 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 6.67) ; Number of LABs (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu Aug 29 08:48:45 2013
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lbstry -c lbstry
Info: Selected device EP1C3T144C8 for design "lbstry"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "CLK" to use Global clock in PIN 47
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 6.013 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y1; Fanout = 4; REG Node = '74161:inst|f74161:sub|9'
Info: 2: + IC(0.377 ns) + CELL(0.590 ns) = 0.967 ns; Loc. = LAB_X4_Y1; Fanout = 7; COMB Node = 'inst9~70'
Info: 3: + IC(0.075 ns) + CELL(0.590 ns) = 1.632 ns; Loc. = LAB_X4_Y1; Fanout = 6; COMB Node = 'inst15~24'
Info: 4: + IC(0.223 ns) + CELL(0.442 ns) = 2.297 ns; Loc. = LAB_X4_Y1; Fanout = 5; COMB Node = 'inst17~20'
Info: 5: + IC(0.223 ns) + CELL(0.442 ns) = 2.962 ns; Loc. = LAB_X4_Y1; Fanout = 4; COMB Node = 'inst17'
Info: 6: + IC(0.223 ns) + CELL(0.442 ns) = 3.627 ns; Loc. = LAB_X4_Y1; Fanout = 2; COMB Node = '74161:inst3|f74161:sub|80'
Info: 7: + IC(0.075 ns) + CELL(0.590 ns) = 4.292 ns; Loc. = LAB_X4_Y1; Fanout = 2; COMB Node = '74161:inst3|f74161:sub|84'
Info: 8: + IC(0.599 ns) + CELL(0.292 ns) = 5.183 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = '74161:inst3|f74161:sub|97~3'
Info: 9: + IC(0.223 ns) + CELL(0.607 ns) = 6.013 ns; Loc. = LAB_X5_Y1; Fanout = 3; REG Node = '74161:inst3|f74161:sub|99'
Info: Total cell delay = 3.995 ns ( 66.44 % )
Info: Total interconnect delay = 2.018 ns ( 33.56 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Aug 29 08:48:48 2013
Info: Elapsed time: 00:00:03
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