2410addr.inc

武汉创维特的arm培训例程试验程序

@====================================================================
@ File Name : 2410addr.a
@ Function  : S3C2410 Define Address Register (Assembly)
@ Program   : Shin, On Pil (SOP)
@ Date      : March 27, 2002
@ Version   : 0.0
@ History
@   1.0 : Programming start (February 18,2002) -> SOP
@         INTERRUPT rPRIORITY 0x4a00000a -> 0x4a00000c       (May 06, 2002 SOP)
@         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP) 
@====================================================================


@=================
@ Memory control 
@=================
.EQU    BWSCON      ,  0x48000000     @Bus width & wait status
.EQU    BANKCON0    ,  0x48000004     @Boot ROM control
.EQU    BANKCON1    ,  0x48000008     @BANK1 control
.EQU    BANKCON2    ,  0x4800000c     @BANK2 cControl
.EQU    BANKCON3    ,  0x48000010     @BANK3 control
.EQU    BANKCON4    ,  0x48000014     @BANK4 control
.EQU    BANKCON5    ,  0x48000018     @BANK5 control
.EQU    BANKCON6    ,  0x4800001c     @BANK6 control
.EQU    BANKCON7    ,  0x48000020     @BANK7 control
.EQU    REFRESH     ,  0x48000024     @DRAM/SDRAM refresh
.EQU    BANKSIZE    ,  0x48000028     @Flexible Bank Size
.EQU    MRSRB6      ,  0x4800002c     @Mode register set for SDRAM
.EQU    MRSRB7      ,  0x48000030     @Mode register set for SDRAM

@=================
@ USB Host
@=================

@=================
@ INTERRUPT
@=================
.EQU    SRCPND       ,  0x4a000000    @Interrupt request status
.EQU    INTMOD       ,  0x4a000004    @Interrupt mode control
.EQU    INTMSK       ,  0x4a000008    @Interrupt mask control
.EQU    PRIORITY     ,  0x4a00000a    @IRQ priority control
.EQU    INTPND       ,  0x4a000010    @Interrupt request status
.EQU    INTOFFSET    ,  0x4a000014    @Interruot request source offset
.EQU    SUSSRCPND    ,  0x4a000018    @Sub source pending
.EQU    INTSUBMSK    ,  0x4a00001c    @Interrupt sub mask


@=================
@ DMA
@=================
.EQU    DISRC0       ,  0x4b000000    @DMA 0 Initial source
.EQU    DISRCC0      ,  0x4b000004    @DMA 0 Initial source control
.EQU    DIDST0       ,  0x4b000008    @DMA 0 Initial Destination
.EQU    DIDSTC0      ,  0x4b00000c    @DMA 0 Initial Destination control
.EQU    DCON0        ,  0x4b000010    @DMA 0 Control
.EQU    DSTAT0       ,  0x4b000014    @DMA 0 Status
.EQU    DCSRC0       ,  0x4b000018    @DMA 0 Current source
.EQU    DCDST0       ,  0x4b00001c    @DMA 0 Current destination
.EQU    DMASKTRIG0   ,  0x4b000020    @DMA 0 Mask trigger

.EQU    DISRC1       ,  0x4b000040    @DMA 1 Initial source
.EQU    DISRCC1      ,  0x4b000044    @DMA 1 Initial source control
.EQU    DIDST1       ,  0x4b000048    @DMA 1 Initial Destination
.EQU    DIDSTC1      ,  0x4b00004c    @DMA 1 Initial Destination control
.EQU    DCON1        ,  0x4b000050    @DMA 1 Control
.EQU    DSTAT1       ,  0x4b000054    @DMA 1 Status
.EQU    DCSRC1       ,  0x4b000058    @DMA 1 Current source
.EQU    DCDST1       ,  0x4b00005c    @DMA 1 Current destination
.EQU    DMASKTRIG1   ,  0x4b000060    @DMA 1 Mask trigger

.EQU    DISRC2       ,  0x4b000080    @DMA 2 Initial source
.EQU    DISRCC2      ,  0x4b000084    @DMA 2 Initial source control
.EQU    DIDST2       ,  0x4b000088    @DMA 2 Initial Destination
.EQU    DIDSTC2      ,  0x4b00008c    @DMA 2 Initial Destination control
.EQU    DCON2        ,  0x4b000090    @DMA 2 Control
.EQU    DSTAT2       ,  0x4b000094    @DMA 2 Status
.EQU    DCSRC2       ,  0x4b000098    @DMA 2 Current source
.EQU    DCDST2       ,  0x4b00009c    @DMA 2 Current destination
.EQU    DMASKTRIG2   ,  0x4b0000a0    @DMA 2 Mask trigger

.EQU    DISRC3       ,  0x4b0000c0    @DMA 3 Initial source
.EQU    DISRCC3      ,  0x4b0000c4    @DMA 3 Initial source control
.EQU    DIDST3       ,  0x4b0000c8    @DMA 3 Initial Destination
.EQU    DIDSTC3      ,  0x4b0000cc    @DMA 3 Initial Destination control
.EQU    DCON3        ,  0x4b0000d0    @DMA 3 Control
.EQU    DSTAT3       ,  0x4b0000d4    @DMA 3 Status
.EQU    DCSRC3       ,  0x4b0000d8    @DMA 3 Current source
.EQU    DCDST3       ,  0x4b0000dc    @DMA 3 Current destination
.EQU    DMASKTRIG3   ,  0x4b0000e0    @DMA 3 Mask trigger


@==========================
@ CLOCK & POWER MANAGEMENT
@==========================
.EQU    LOCKTIME    ,  0x4c000000     @PLL lock time counter
.EQU    MPLLCON     ,  0x4c000004     @MPLL Control
.EQU    UPLLCON     ,  0x4c000008     @UPLL Control
.EQU    CLKCON      ,  0x4c00000c     @Clock generator control
.EQU    CLKSLOW     ,  0x4c000010     @Slow clock control
.EQU    CLKDIVN     ,  0x4c000014     @Clock divider control


@=================
@ LCD CONTROLLER
@=================
.EQU    LCDCON1     ,  0x4d000000     @LCD control 1
.EQU    LCDCON2     ,  0x4d000004     @LCD control 2
.EQU    LCDCON3     ,  0x4d000008     @LCD control 3
.EQU    LCDCON4     ,  0x4d00000c     @LCD control 4
.EQU    LCDCON5     ,  0x4d000010     @LCD control 5
.EQU    LCDSADDR1   ,  0x4d000014     @STN/TFT Frame buffer start address 1
.EQU    LCDSADDR2   ,  0x4d000018     @STN/TFT Frame buffer start address 2
.EQU    LCDSADDR3   ,  0x4d00001c     @STN/TFT Virtual screen address set
.EQU    REDLUT      ,  0x4d000020     @STN Red lookup table
.EQU    GREENLUT    ,  0x4d000024     @STN Green lookup table 
.EQU    BLUELUT     ,  0x4d000028     @STN Blue lookup table
.EQU    DITHMODE    ,  0x4d00004c     @STN Dithering mode
.EQU    TPAL        ,  0x4d000050     @TFT Temporary palette
.EQU    LCDINTPND   ,  0x4d000054     @LCD Interrupt pending
.EQU    LCDSRCPND   ,  0x4d000058     @LCD Interrupt source
.EQU    LCDINTMSK   ,  0x4d00005c     @LCD Interrupt mask
.EQU    LPCSEL      ,  0x4d000060     @LPC3600 Control


@=================
@ NAND flash
@=================
.EQU    NFCONF      ,  0x4e000000     @NAND Flash configuration
.EQU    NFCMD       ,  0x4e000004     @NADD Flash command
.EQU    NFADDR      ,  0x4e000008     @NAND Flash address
.EQU    NFDATA      ,  0x4e00000c     @NAND Flash data
.EQU    NFSTAT      ,  0x4e000010     @NAND Flash operation status
.EQU    NFECC       ,  0x4e000014     @NAND Flash ECC


@=================
@ UART
@=================
.EQU    ULCON0       ,  0x50000000    @UART 0 Line control
.EQU    UCON0        ,  0x50000004    @UART 0 Control
.EQU    UFCON0       ,  0x50000008    @UART 0 FIFO control
.EQU    UMCON0       ,  0x5000000c    @UART 0 Modem control
.EQU    UTRSTAT0     ,  0x50000010    @UART 0 Tx/Rx status
.EQU    UERSTAT0     ,  0x50000014    @UART 0 Rx error status
.EQU    UFSTAT0      ,  0x50000018    @UART 0 FIFO status
.EQU    UMSTAT0      ,  0x5000001c    @UART 0 Modem status
.EQU    UBRDIV0      ,  0x50000028    @UART 0 Baud rate divisor

.EQU    ULCON1       ,  0x50004000    @UART 1 Line control
.EQU    UCON1        ,  0x50004004    @UART 1 Control
.EQU    UFCON1       ,  0x50004008    @UART 1 FIFO control
.EQU    UMCON1       ,  0x5000400c    @UART 1 Modem control
.EQU    UTRSTAT1     ,  0x50004010    @UART 1 Tx/Rx status
.EQU    UERSTAT1     ,  0x50004014    @UART 1 Rx error status
.EQU    UFSTAT1      ,  0x50004018    @UART 1 FIFO status
.EQU    UMSTAT1      ,  0x5000401c    @UART 1 Modem status
.EQU    UBRDIV1      ,  0x50004028    @UART 1 Baud rate divisor

.EQU    ULCON2       ,  0x50008000    @UART 2 Line control
.EQU    UCON2        ,  0x50008004    @UART 2 Control
.EQU    UFCON2       ,  0x50008008    @UART 2 FIFO control
.EQU    UMCON2       ,  0x5000800c    @UART 2 Modem control
.EQU    UTRSTAT2     ,  0x50008010    @UART 2 Tx/Rx status
.EQU    UERSTAT2     ,  0x50008014    @UART 2 Rx error status
.EQU    UFSTAT2      ,  0x50008018    @UART 2 FIFO status
.EQU    UMSTAT2      ,  0x5000801c    @UART 2 Modem status
.EQU    UBRDIV2      ,  0x50008028    @UART 2 Baud rate divisor

.IFDEF BIG_ENDIAN__
.EQU    UTXH0        ,  0x50000023    @UART 0 Transmission Hold
.EQU    URXH0        ,  0x50000027    @UART 0 Receive buffer
.EQU    UTXH1        ,  0x50004023    @UART 1 Transmission Hold
.EQU    URXH1        ,  0x50004027    @UART 1 Receive buffer
.EQU    UTXH2        ,  0x50008023    @UART 2 Transmission Hold
.EQU    URXH2        ,  0x50008027    @UART 2 Receive buffer

.ELSE                               @Little Endian
.EQU    UTXH0        ,  0x50000020    @UART 0 Transmission Hold
.EQU    URXH0        ,  0x50000024    @UART 0 Receive buffer
.EQU    UTXH1        ,  0x50004020    @UART 1 Transmission Hold
.EQU    URXH1        ,  0x50004024    @UART 1 Receive buffer
.EQU    UTXH2        ,  0x50008020    @UART 2 Transmission Hold
.EQU    URXH2        ,  0x50008024    @UART 2 Receive buffer
.ENDIF


@=================
@ PWM TIMER
@=================
.EQU    TCFG0    ,  0x51000000        @Timer 0 configuration
.EQU    TCFG1    ,  0x51000004        @Timer 1 configuration
.EQU    TCON     ,  0x51000008        @Timer control
.EQU    TCNTB0   ,  0x5100000c        @Timer count buffer 0
.EQU    TCMPB0   ,  0x51000010        @Timer compare buffer 0
.EQU    TCNTO0   ,  0x51000014        @Timer count observation 0
.EQU    TCNTB1   ,  0x51000018        @Timer count buffer 1
.EQU    TCMPB1   ,  0x5100001c        @Timer compare buffer 1
.EQU    TCNTO1   ,  0x51000020        @Timer count observation 1
.EQU    TCNTB2   ,  0x51000024        @Timer count buffer 2
.EQU    TCMPB2   ,  0x51000028        @Timer compare buffer 2
.EQU    TCNTO2   ,  0x5100002c        @Timer count observation 2
.EQU    TCNTB3   ,  0x51000030        @Timer count buffer 3
.EQU    TCMPB3   ,  0x51000034        @Timer compare buffer 3
.EQU    TCNTO3   ,  0x51000038        @Timer count observation 3
.EQU    TCNTB4   ,  0x5100003c        @Timer count buffer 4
.EQU    TCNTO4   ,  0x51000040        @Timer count observation 4


@=================
@ USB DEVICE
@=================
.IFDEF         BIG_ENDIAN__
.EQU    FUNC_ADDR_REG       ,  0x52000143     @Function address
.EQU    PWR_REG             ,  0x52000147     @Power management
.EQU    EP_INT_REG          ,  0x5200014b     @EP Interrupt pending and clear
.EQU    USB_INT_REG         ,  0x5200015b     @USB Interrupt pending and clear
.EQU    EP_INT_EN_REG       ,  0x5200015f     @Interrupt enable
.EQU    USB_INT_EN_REG      ,  0x5200016f
.EQU    FRAME_NUM1_REG      ,  0x52000173     @Frame number lower byte
.EQU    FRAME_NUM2_REG      ,  0x52000177     @Frame number lower byte
.EQU    INDEX_REG           ,  0x5200017b     @Register index
.EQU    MAXP_REG            ,  0x52000183     @Endpoint max packet
.EQU    EP0_CSR             ,  0x52000187     @Endpoint 0 status
.EQU    IN_CSR1_REG         ,  0x52000187     @In endpoint control status
.EQU    IN_CSR2_REG         ,  0x5200018b
.EQU    OUT_CSR1_REG        ,  0x52000193     @Out endpoint control status
.EQU    OUT_CSR2_REG        ,  0x52000197
.EQU    OUT_FIFO_CNT1_REG   ,  0x5200019b     @Endpoint out write count
.EQU    OUT_FIFO_CNT2_REG   ,  0x5200019f
.EQU    EP0_FIFO            ,  0x520001c3     @Endpoint 0 FIFO
.EQU    EP1_FIFO            ,  0x520001c7     @Endpoint 1 FIFO
.EQU    EP2_FIFO            ,  0x520001cb     @Endpoint 2 FIFO
.EQU    EP3_FIFO            ,  0x520001cf     @Endpoint 3 FIFO
.EQU    EP4_FIFO            ,  0x520001d3     @Endpoint 4 FIFO
.EQU    EP1_DMA_CON         ,  0x52000203     @EP1 DMA interface control
.EQU    EP1_DMA_UNIT        ,  0x52000207     @EP1 DMA Tx unit counter
.EQU    EP1_DMA_FIFO        ,  0x5200020b     @EP1 DMA Tx FIFO counter
.EQU    EP1_DMA_TTC_L       ,  0x5200020f     @EP1 DMA total Tx counter
.EQU    EP1_DMA_TTC_M       ,  0x52000213
.EQU    EP1_DMA_TTC_H       ,  0x52000217
.EQU    EP2_DMA_CON         ,  0x5200021b     @EP2 DMA interface control
.EQU    EP2_DMA_UNIT        ,  0x5200021f     @EP2 DMA Tx unit counter
.EQU    EP2_DMA_FIFO        ,  0x52000223     @EP2 DMA Tx FIFO counter
.EQU    EP2_DMA_TTC_L       ,  0x52000227     @EP2 DMA total Tx counter
.EQU    EP2_DMA_TTC_M       ,  0x5200022b
.EQU    EP2_DMA_TTC_H       ,  0x5200022f
.EQU    EP3_DMA_CON         ,  0x52000243     @EP3 DMA interface control
.EQU    EP3_DMA_UNIT        ,  0x52000247     @EP3 DMA Tx unit counter
.EQU    EP3_DMA_FIFO        ,  0x5200024b     @EP3 DMA Tx FIFO counter
.EQU    EP3_DMA_TTC_L       ,  0x5200024f     @EP3 DMA total Tx counter
.EQU    EP3_DMA_TTC_M       ,  0x52000253
.EQU    EP3_DMA_TTC_H       ,  0x52000257
.EQU    EP4_DMA_CON         ,  0x5200025b     @EP4 DMA interface control
.EQU    EP4_DMA_UNIT        ,  0x5200025f     @EP4 DMA Tx unit counter
.EQU    EP4_DMA_FIFO        ,  0x52000263     @EP4 DMA Tx FIFO counter
.EQU    EP4_DMA_TTC_L       ,  0x52000267     @EP4 DMA total Tx counter
.EQU    EP4_DMA_TTC_M       ,  0x5200026b
.EQU    EP4_DMA_TTC_H       ,  0x5200026f

.ELSE           @ Little Endian
.EQU    FUNC_ADDR_REG       ,  0x52000140     @Function address
.EQU    PWR_REG             ,  0x52000144     @Power management
.EQU    EP_INT_REG          ,  0x52000148     @EP Interrupt pending and clear
.EQU    USB_INT_REG         ,  0x52000158     @USB Interrupt pending and clear
.EQU    EP_INT_EN_REG       ,  0x5200015c     @Interrupt enable
.EQU    USB_INT_EN_REG      ,  0x5200016c
.EQU    FRAME_NUM1_REG      ,  0x52000170     @Frame number lower byte
.EQU    FRAME_NUM2_REG      ,  0x52000174     @Frame number lower byte
.EQU    INDEX_REG           ,  0x52000178     @Register index
.EQU    MAXP_REG            ,  0x52000180     @Endpoint max packet
.EQU    EP0_CSR             ,  0x52000184     @Endpoint 0 status
.EQU    IN_CSR1_REG         ,  0x52000184     @In endpoint control status
.EQU    IN_CSR2_REG         ,  0x52000188
.EQU    OUT_CSR1_REG        ,  0x52000190     @Out endpoint control status
.EQU    OUT_CSR2_REG        ,  0x52000194
.EQU    OUT_FIFO_CNT1_REG   ,  0x52000198     @Endpoint out write count
.EQU    OUT_FIFO_CNT2_REG   ,  0x5200019c
.EQU    EP0_FIFO            ,  0x520001c0     @Endpoint 0 FIFO
.EQU    EP1_FIFO            ,  0x520001c4     @Endpoint 1 FIFO
.EQU    EP2_FIFO            ,  0x520001c8     @Endpoint 2 FIFO
.EQU    EP3_FIFO            ,  0x520001cc     @Endpoint 3 FIFO
.EQU    EP4_FIFO            ,  0x520001d0     @Endpoint 4 FIFO
.EQU    EP1_DMA_CON         ,  0x52000200     @EP1 DMA interface control
.EQU    EP1_DMA_UNIT        ,  0x52000204     @EP1 DMA Tx unit counter
.EQU    EP1_DMA_FIFO        ,  0x52000208     @EP1 DMA Tx FIFO counter
.EQU    EP1_DMA_TTC_L       ,  0x5200020c     @EP1 DMA total Tx counter
.EQU    EP1_DMA_TTC_M       ,  0x52000210
.EQU    EP1_DMA_TTC_H       ,  0x52000214