os_cpu_a.~s

武汉创维特的arm培训例程试验程序

	LDR	r5, [r4]
	STR	sp, [r5]		@ store sp in preempted tasks's TCB

	@ Get highest priority task TCB address
	LDR	r6, addr_OSTCBHighRdy
	LDR	r6, [r6]
	LDR	sp, [r6]		@ get new task's stack pointer

	@ OSTCBCur = OSTCBHighRdy
	STR	r6, [r4]		@ set new current task TCB address

	LDMFD	sp!, {r4}		@ YYY+
	MSR	SPSR_cxsf, r4		@ YYY+
	LDMFD	sp!, {r4}		@ YYY+
	MSR	CPSR_cxsf, r4		@ YYY+
	LDMFD	sp!, {r0-r12, lr, pc}	@ YYY+


SAVED_LR:
	.LONG  0
@/*************************************************************************/
@/*                                                                       */
@/* FUNCTION                                                              */
@/*                                                                       */
@/*      ARMDisableInt                                                    */
@/*                                                                       */
@/* DESCRIPTION                                                           */
@/*                                                                       */
@/*      Disable IRQ and FIQ preserving current CPU mode.                 */
@/*                                                                       */
@/*             - Set CPSR bit7 to disable IRQ                            */
@/*                                                                       */
@/* AUTHOR                                                                */
@/*                                                                       */
@/*      @                                                     */
@/* DATE:                                                                 */
@/*      2003-06-05                                                       */
@/* CALLED BY                                                             */
@/*                                                                       */
@/*                                                                       */
@/* CALLS                                                                 */
@/*                                                                       */
@/*      none                                                             */
@/*                                                                       */
@/* INPUTS                                                                */
@/*                                                                       */
@/*      None                                                             */
@/*                                                                       */
@/* OUTPUTS                                                               */
@/*                                                                       */
@/*      None                                                             */
@/*                                                                       */
@/* HISTORY                                                               */
@/*                                                                       */
@/*         NAME            DATE                    REMARKS               */
@/*                                                                       */
@/*                                                                       */
@/*************************************************************************/
@VOID    ARMDisableInt(void)
@{
	.GLOBAL	ARMDisableInt
ARMDisableInt:
	STMDB	sp!, {r0}
	MRS		r0, CPSR
	ORR		r0, r0, #NoInt
	MSR		CPSR_cxsf, r0
	LDMIA	sp!, {r0}
	MOV	pc, lr



@/*************************************************************************/
@/*                                                                       */
@/* FUNCTION                                                              */
@/*                                                                       */
@/*      ARMEnableInt                                                     */
@/*                                                                       */
@/* DESCRIPTION                                                           */
@/*                                                                       */
@/*      Enable IRQ and FIQ preserving current CPU mode.                  */
@/*                                                                       */
@/*             - Clear CPSR bit7 to enable IRQ                           */
@/*                                                                       */
@/* AUTHOR                                                                */
@/*                                                                       */
@/*      @                                                     */
@/* DATE:                                                                 */
@/*      2003-06-05                                                       */
@/* CALLED BY                                                             */
@/*                                                                       */
@/*                                                                       */
@/* CALLS                                                                 */
@/*                                                                       */
@/*      none                                                             */
@/*                                                                       */
@/* INPUTS                                                                */
@/*                                                                       */
@/*      None                                                             */
@/*                                                                       */
@/* OUTPUTS                                                               */
@/*                                                                       */
@/*      None                                                             */
@/*                                                                       */
@/* HISTORY                                                               */
@/*                                                                       */
@/*         NAME            DATE                    REMARKS               */
@/*                                                                       */
@/*                                                                       */
@/*************************************************************************/
@VOID    ARMEnableInt(void)
@{
	.GLOBAL	ARMEnableInt
ARMEnableInt:
	STMDB	sp!, {r0}
	MRS	r0, CPSR
	BIC	r0, r0, #NoInt
	MSR	CPSR_cxsf, r0
	LDMIA	sp!, {r0}
	MOV	pc, lr



@	void OS_TASK_SW(void)
@	
@	Perform a context switch.
@
@	On entry, OSTCBCur and OSPrioCur hold the current TCB and priority
@	and OSTCBHighRdy and OSPrioHighRdy contain the same for the task
@	to be switched to.
@
@	The following code assumes that the virtual memory is directly
@	mapped into  physical memory. If this is not true, the cache must 
@	be flushed at context switch to avoid address aliasing.
	.GLOBAL	OS_TASK_SW
OS_TASK_SW:
	STMFD	sp!, {lr}		@ save pc
	STMFD	sp!, {lr}		@ save lr
	STMFD	sp!, {r0-r12}	@ save register file and ret address
	MRS	r4, CPSR
	STMFD	sp!, {r4}		@ save current PSR
	MRS	r4, SPSR		@ YYY+
	STMFD	sp!, {r4}		@ YYY+ save SPSR

	@ OSPrioCur = OSPrioHighRdy
	LDR	r4, addr_OSPrioCur
	LDR	r5, addr_OSPrioHighRdy
	LDRB	r6, [r5]
	STRB	r6, [r4]
	
	@ Get current task TCB address
	LDR	r4, addr_OSTCBCur
	LDR	r5, [r4]
	STR	sp, [r5]		@ store sp in preempted tasks's TCB

	@ Get highest priority task TCB address
	LDR	r6, addr_OSTCBHighRdy
	LDR	r6, [r6]
	LDR	sp, [r6]		@ get new task's stack pointer

	@ OSTCBCur = OSTCBHighRdy
	STR	r6, [r4]		@ set new current task TCB address

	LDMFD	sp!, {r4}		@ YYY+
	MSR	SPSR_cxsf, r4		@ YYY+
	LDMFD	sp!, {r4}		@ YYY+
	MSR	CPSR_cxsf, r4		@ YYY+
	LDMFD	sp!, {r0-r12, lr, pc}	@ YYY+



@	void OSStartHighRdy(void)
@	
@	Start the task with the highest priority@
@
	.GLOBAL	OSStartHighRdy
OSStartHighRdy:
	LDR	r4, addr_OSTCBCur	@ Get current task TCB address
	LDR	r5, addr_OSTCBHighRdy	@ Get highest priority task TCB address

	LDR	r5, [r5]		@ get stack pointer
	LDR	sp, [r5]		@ switch to the new stack

	STR	r5, [r4]		@ set new current task TCB address

	LDMFD	sp!, {r4}		@ YYY
	MSR	SPSR_cxsf, r4
	LDMFD	sp!, {r4}		@ get new state from top of the stack
	MSR	CPSR_cxsf, r4		@ CPSR should be SVC32Mode
	LDMFD	sp!, {r0-r12, lr, pc }	@ start the new task

	.END