c_can.c

HMS30C7202下的CAN驱动

                                                          pmsgobj->hostchip, CCIF1M2);
                else
                        pmsgobj->hostchip->write_register(((mask<<2) & 0x1FFC), pmsgobj->hostchip,
                                                          CCIF1M2);
                        pmsgobj->hostchip->write_register(0, pmsgobj->hostchip, CCIF1M1);
        }
        /* seting Message Valid Bit to one */
        tempreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1A2);
        pmsgobj->hostchip->write_register(tempreg | IFXARB2_MVAL, pmsgobj->hostchip, CCIF1A2);
        /* write to chip */
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);

        spin_unlock( &pmsgobj->hostchip->if1lock );

        DEBUGMSG(" -> Setting acceptance mask to 0x%lx",(unsigned long)mask);

#ifdef REGDUMP
        c_can_registerdump(pmsgobj->hostchip);
#endif

        return 0;
}

///////////////////////////////////////////////////////////////////////
/**
 * Through this function the mask filtering function can be activated and
 * deactivated
 */
int c_can_use_mask(struct msgobj_t *pmsgobj,
                   u16 useflag)
{
        unsigned short tempreg = 0;
        unsigned short readMaskCM;
        unsigned short writeMaskCM;

#ifdef DEBUG
        char *boolstring = "false";
        if (useflag) boolstring = "true";
#endif
        DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)", pmsgobj->hostchip->chip_nr, pmsgobj->object);

        readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
        writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;

        spin_lock( &pmsgobj->hostchip->if1lock );

        /* load Message Object in IF1 */
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        pmsgobj->hostchip->write_register(readMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);

        /* setting Message Valid Bit to zero */
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        tempreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1A2);
        pmsgobj->hostchip->write_register(tempreg & ~IFXARB2_MVAL, pmsgobj->hostchip, CCIF1A2);
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);

        /* setting UMask bit */
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        if ( useflag ) {
                tempreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1DMC);
                pmsgobj->hostchip->write_register(tempreg | IFXMC_UMASK, pmsgobj->hostchip, CCIF1DMC);
        } else {
                tempreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1DMC);
                pmsgobj->hostchip->write_register(tempreg & ~IFXMC_UMASK, pmsgobj->hostchip, CCIF1DMC);
        }
        /* seting Message Valid Bit to one */
        tempreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1A2);
        pmsgobj->hostchip->write_register(tempreg | IFXARB2_MVAL, pmsgobj->hostchip, CCIF1A2);
        /* write to chip */
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);

        spin_unlock( &pmsgobj->hostchip->if1lock );

#ifdef DEBUG
        DEBUGMSG(" -> Setting umask bit to %s",boolstring);
#endif
#ifdef REGDUMP
        c_can_registerdump(pmsgobj->hostchip);
#endif

        return 0;
}

///////////////////////////////////////////////////////////////////////
/**
 * This function sets all message objects to invalid and reinitializes
 * their I/O buffers.
 */
int c_can_clear_objects(struct chip_t *pchip)
{
        unsigned short i = 0;
        unsigned short tempreg = 0;

        unsigned short maskCM = IFXCM_ARB;

        DEBUGMSG("(c%d)calling c_can_clear_objects(...)", pchip->chip_nr);

        spin_lock( &pchip->if1lock );
        spin_lock( &pchip->if2lock );

        for (i=0; i<0x10; i++) {

                /* loading Message Objects in IF1 and IF2 */
                if (c_can_if1_busycheck(pchip)) return -ENODEV;
                pchip->write_register(maskCM, pchip, CCIF1CM);
                pchip->write_register(i, pchip, CCIF1CR);
                if (c_can_if2_busycheck(pchip)) return -ENODEV;
                pchip->write_register(maskCM, pchip, CCIF2CM);
                pchip->write_register(i+0x10, pchip, CCIF2CR);

                /* setting Message Valid Bit to zero */
                if (c_can_if1_busycheck(pchip)) return -ENODEV;
                tempreg = pchip->read_register(pchip, CCIF1A2);
                pchip->write_register(tempreg & ~IFXARB2_MVAL, pchip, CCIF1A2);
                pchip->write_register(i, pchip, CCIF1CR);
                if (c_can_if2_busycheck(pchip)) return -ENODEV;
                tempreg = pchip->read_register(pchip, CCIF2A2);
                pchip->write_register(tempreg & ~IFXARB2_MVAL, pchip, CCIF2A2);
                pchip->write_register(i+0x10, pchip, CCIF2CR);
        }

        for (i=0; i<pchip->obj_cnt; i++) {
                if (pchip->pmsgobj[i]->flags & CHANNEL_OPENED) {
                        /* In- and output buffer re-initialization */
                        pchip->pmsgobj[i]->fifo->txrp = pchip->pmsgobj[i]->fifo->ptxbuf;
                        pchip->pmsgobj[i]->fifo->txwp = pchip->pmsgobj[i]->fifo->ptxbuf;
                        pchip->pmsgobj[i]->fifo->rxrp = pchip->pmsgobj[i]->fifo->prxbuf;
                        pchip->pmsgobj[i]->fifo->rxwp = pchip->pmsgobj[i]->fifo->prxbuf;
                        pchip->pmsgobj[i]->fifo->rxsize = MAX_BUF_LENGTH * sizeof( struct canmsg_t );
                        pchip->pmsgobj[i]->fifo->txsize = MAX_BUF_LENGTH * sizeof( struct canmsg_t );

                        init_waitqueue_head( &pchip->pmsgobj[i]->fifo->readq );
                        init_waitqueue_head( &pchip->pmsgobj[i]->fifo->writeq  );

                        pchip->pmsgobj[i]->fifo->flags &= ~(TX_IN_PROGRESS | RX_IN_PROGRESS);

                        pchip->pmsgobj[i]->fifo->head = pchip->pmsgobj[i]->fifo->tail = 0;  //TEMP!!
                }
        }

        spin_unlock( &pchip->if1lock );
        spin_unlock( &pchip->if2lock );

        DEBUGMSG(" -> Message Objects reset");

        return 0;
}

///////////////////////////////////////////////////////////////////////
/**
 * Through this function the three IRQ-flags (IE, SIE, EIE) can be set.
 */
int c_can_config_irqs(struct chip_t *pchip,
                      u16 irqs)
{
        u16 tempreg;

        DEBUGMSG("(c%d)calling c_can_config_irqs(...)", pchip->chip_nr);

        /*
         * CANMSG("c_can_config_irqs not implemented\n");
         * return -ENOSYS;
         */

        tempreg = pchip->read_register( pchip, CCCR );
        //DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
        pchip->write_register( ( tempreg & 0xf1 ) | ( irqs & 0xe ), pchip, CCCR );
        DEBUGMSG(" -> Configured hardware interrupt delivery");
        return 0;
}

///////////////////////////////////////////////////////////////////////
/**
 * Configures a message object to receive messages and sets the ID bits.
 */
int c_can_pre_read_config(struct msgobj_t *pmsgobj, u32 id)
{
        unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
        unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
        unsigned short mcreg = 0;

        DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)", pmsgobj->hostchip->chip_nr, pmsgobj->object);

        spin_lock( &pmsgobj->hostchip->if1lock );

        pmsgobj->flags |= CHANNEL_RECEIVE;

        //loading Message Object in IF1
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        pmsgobj->hostchip->write_register(readMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);
        //setting Message Valid Bit to zero
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        pmsgobj->hostchip->write_register(0, pmsgobj->hostchip, CCIF1A2);
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);
        //Configuring Message-Object
        if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
        mcreg = pmsgobj->hostchip->read_register(pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE),
                                          pmsgobj->hostchip, CCIF1DMC);
        //writing arbitration mask for extended or standart mode
        if (pmsgobj->msg_mode & 1) {
                pmsgobj->hostchip->write_register(IFXARB2_XTD | IFXARB2_MVAL | (id>>16 & 0x1FFF),
                                                  pmsgobj->hostchip, CCIF1A2);
                pmsgobj->hostchip->write_register(id & 0xFFFF, pmsgobj->hostchip, CCIF1A1);
        } else {
                pmsgobj->hostchip->write_register(IFXARB2_MVAL | (id<<2 & 0x1FFC),
                                                  pmsgobj->hostchip, CCIF1A2);
                //pmsgobj->hostchip->write_register(0, pmsgobj->hostchip, CCIF1A1);
        }
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF1CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF1CR);

        spin_unlock( &pmsgobj->hostchip->if1lock );

        DEBUGMSG(" -> Receiving through message object %d with id=%d", pmsgobj->object+1,
                 id);
#ifdef REGDUMP
        c_can_registerdump(pmsgobj->hostchip);
#endif

        return 0;
}

///////////////////////////////////////////////////////////////////////
/**
 * Send specified Message over specified Messageobject
 */
int c_can_send_msg(struct msgobj_t *pmsgobj,
                   struct canmsg_t *pmsg)
{
        unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
        unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD;
        unsigned short writeSendMskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD
                                        | IFXCM_TRND;
        unsigned short mcreg = 0;
        //unsigned short arbreg = 0;
        unsigned short dataA1 = 0;
        unsigned short dataA2 = 0;
        unsigned short dataB1 = 0;
        unsigned short dataB2 = 0;

        DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)", pmsgobj->hostchip->chip_nr, pmsgobj->object);

        spin_lock( &pmsgobj->hostchip->if2lock );

        pmsgobj->flags |= ~CHANNEL_RECEIVE;

        //loading Message Object in IF1
        if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
        pmsgobj->hostchip->write_register(readMaskCM, pmsgobj->hostchip, CCIF2CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF2CR);
        //setting Message Valid Bit to zero
        if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
        pmsgobj->hostchip->write_register(0, pmsgobj->hostchip, CCIF2A2);
        pmsgobj->hostchip->write_register(writeMaskCM, pmsgobj->hostchip, CCIF2CM);
        pmsgobj->hostchip->write_register(pmsgobj->object+1, pmsgobj->hostchip, CCIF2CR);
        //Configuring MO
        if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
        mcreg = pmsgobj->hostchip->read_register( pmsgobj->hostchip, CCIF2CM);
        //remote enable?
        //define Command Mask
        pmsgobj->hostchip->write_register((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE
                                           | IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST
                                           | (pmsg->length & 0xF),
                                           pmsgobj->hostchip, CCIF2DMC);
        //set Arbitration Bits
        if (pmsgobj->msg_mode & 1) {
                pmsgobj->hostchip->write_register((u16)(pmsg->id), pmsgobj->hostchip, CCIF2A1);
                pmsgobj->hostchip->write_register(IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR
                                                  | ((u16)(pmsg->id>>16) & 0x1FFF),
                                                  pmsgobj->hostchip, CCIF2A2);
        } else {
                pmsgobj->hostchip->write_register((IFXARB2_MVAL | IFXARB2_DIR
                                                  | ((u16)(pmsg->id<<2) & 0x1FFC)),
                                                  pmsgobj->hostchip, CCIF2A2);
                pmsgobj->hostchip->write_register(0, pmsgobj->hostchip, CCIF1A1);
        }
        //write Data
        if (pmsg->length>0) {
                dataA1 = pmsg->data[0] | (u16)pmsg->data[1]<<8;
                dataA2 = pmsg->data[2] | (u16)pmsg->data[3]<<8;
                dataB1 = pmsg->data[4] | (u16)pmsg->data[5]<<8;
                dataB2 = pmsg->data[6] | (u16)pmsg->data[7]<<8;