nand_interface.map.rpt

利用MAX II CPLD 实现 NAND 闪存接口

; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                          ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+
; nand_interface.v                 ; yes             ; User Verilog HDL File  ; D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+---------------------------------------------+------------+
; Resource                                    ; Usage      ;
+---------------------------------------------+------------+
; Total logic elements                        ; 11         ;
;     -- Combinational with no register       ; 11         ;
;     -- Register only                        ; 0          ;
;     -- Combinational with a register        ; 0          ;
;                                             ;            ;
; Logic element usage by number of LUT inputs ;            ;
;     -- 4 input functions                    ; 6          ;
;     -- 3 input functions                    ; 5          ;
;     -- 2 input functions                    ; 0          ;
;     -- 1 input functions                    ; 0          ;
;     -- 0 input functions                    ; 0          ;
;                                             ;            ;
; Logic elements by mode                      ;            ;
;     -- normal mode                          ; 11         ;
;     -- arithmetic mode                      ; 0          ;
;     -- qfbk mode                            ; 0          ;
;     -- register cascade mode                ; 0          ;
;     -- synchronous clear/load mode          ; 0          ;
;     -- asynchronous clear/load mode         ; 0          ;
;                                             ;            ;
; Total registers                             ; 0          ;
; I/O pins                                    ; 13         ;
; Maximum fan-out node                        ; h_cntrl[0] ;
; Maximum fan-out                             ; 7          ;
; Total fan-out                               ; 46         ;
; Average fan-out                             ; 1.92       ;
+---------------------------------------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |nand_interface            ; 11 (11)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 13   ; 0            ; 11 (11)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |nand_interface     ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; int_ce                                             ; decod6              ; yes                    ;
; int_ale                                            ; decod3              ; yes                    ;
; int_se                                             ; decod4              ; yes                    ;
; int_wp                                             ; decod5              ; yes                    ;
; Number of user-specified and inferred latches = 4  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; Analysis & Synthesis INI Usage                                 ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:56:17 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nand_interface -c nand_interface
Info: Found 1 design units, including 1 entities, in source file nand_interface.v
    Info: Found entity 1: nand_interface
Info: Elaborating entity "nand_interface" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at nand_interface.v(42): object "decod7" assigned a value but never read
Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(67): inferring latch(es) for variable "int_ale", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(79): inferring latch(es) for variable "int_se", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(91): inferring latch(es) for variable "int_wp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(103): inferring latch(es) for variable "int_ce", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "int_ce" at nand_interface.v(103)
Info (10041): Inferred latch for "int_wp" at nand_interface.v(91)
Info (10041): Inferred latch for "int_se" at nand_interface.v(79)
Info (10041): Inferred latch for "int_ale" at nand_interface.v(67)
Info: Implemented 24 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 7 output pins
    Info: Implemented 11 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Thu Nov 22 16:56:20 2007
    Info: Elapsed time: 00:00:03