nand_interface.tan.qmsg

利用MAX II CPLD 实现 NAND 闪存接口

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 22 16:56:28 2007 " "Info: Processing started: Thu Nov 22 16:56:28 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off nand_interface -c nand_interface " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off nand_interface -c nand_interface" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "int_ce " "Warning: Node \"int_ce\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_ale " "Warning: Node \"int_ale\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_se " "Warning: Node \"int_se\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_wp " "Warning: Node \"int_wp\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[0\] " "Info: Assuming node \"h_cntrl\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[1\] " "Info: Assuming node \"h_cntrl\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[2\] " "Info: Assuming node \"h_cntrl\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}