prev_cmp_nand_interface.qmsg

利用MAX II CPLD 实现 NAND 闪存接口

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off nand_interface -c nand_interface " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off nand_interface -c nand_interface" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "int_ce " "Warning: Node \"int_ce\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_ale " "Warning: Node \"int_ale\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_se " "Warning: Node \"int_se\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "int_wp " "Warning: Node \"int_wp\" is a latch" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 91 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[0\] " "Info: Assuming node \"h_cntrl\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[1\] " "Info: Assuming node \"h_cntrl\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h_cntrl\[2\] " "Info: Assuming node \"h_cntrl\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "decod5~21 " "Info: Detected gated clock \"decod5~21\" as buffer" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "decod5~21" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "decod4~29 " "Info: Detected gated clock \"decod4~29\" as buffer" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "decod4~29" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "decod3~9 " "Info: Detected gated clock \"decod3~9\" as buffer" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "decod3~9" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "decod6 " "Info: Detected gated clock \"decod6\" as buffer" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "decod6" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "int_ale e_d h_cntrl\[0\] 1.470 ns register " "Info: tsu for register \"int_ale\" (data pin = \"e_d\", clock pin = \"h_cntrl\[0\]\") is 1.470 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.480 ns + Longest pin register " "Info: + Longest pin to register delay is 2.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns e_d 1 PIN PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_43; Fanout = 4; PIN Node = 'e_d'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { e_d } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.462 ns) 2.480 ns int_ale 2 REG LC_X5_Y1_N2 1 " "Info: 2: + IC(1.310 ns) + CELL(0.462 ns) = 2.480 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'int_ale'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.772 ns" { e_d int_ale } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.170 ns ( 47.18 % ) " "Info: Total cell delay = 1.170 ns ( 47.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns ( 52.82 % ) " "Info: Total interconnect delay = 1.310 ns ( 52.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { e_d int_ale } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { e_d {} e_d~combout {} int_ale {} } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.708ns 0.462ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.673 ns + " "Info: + Micro setup delay of destination is 1.673 ns" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "h_cntrl\[0\] destination 2.683 ns - Shortest register " "Info: - Shortest clock path from clock \"h_cntrl\[0\]\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns h_cntrl\[0\] 1 CLK PIN_89 7 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_89; Fanout = 7; CLK Node = 'h_cntrl\[0\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { h_cntrl[0] } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.534 ns) + CELL(0.125 ns) 2.367 ns decod3~9 2 COMB LC_X5_Y1_N1 1 " "Info: 2: + IC(1.534 ns) + CELL(0.125 ns) = 2.367 ns; Loc. = LC_X5_Y1_N1; Fanout = 1; COMB Node = 'decod3~9'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.659 ns" { h_cntrl[0] decod3~9 } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.125 ns) 2.683 ns int_ale 3 REG LC_X5_Y1_N2 1 " "Info: 3: + IC(0.191 ns) + CELL(0.125 ns) = 2.683 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'int_ale'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.316 ns" { decod3~9 int_ale } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.958 ns ( 35.71 % ) " "Info: Total cell delay = 0.958 ns ( 35.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.725 ns ( 64.29 % ) " "Info: Total interconnect delay = 1.725 ns ( 64.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { h_cntrl[0] decod3~9 int_ale } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { h_cntrl[0] {} h_cntrl[0]~combout {} decod3~9 {} int_ale {} } { 0.000ns 0.000ns 1.534ns 0.191ns } { 0.000ns 0.708ns 0.125ns 0.125ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { e_d int_ale } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { e_d {} e_d~combout {} int_ale {} } { 0.000ns 0.000ns 1.310ns } { 0.000ns 0.708ns 0.462ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { h_cntrl[0] decod3~9 int_ale } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { h_cntrl[0] {} h_cntrl[0]~combout {} decod3~9 {} int_ale {} } { 0.000ns 0.000ns 1.534ns 0.191ns } { 0.000ns 0.708ns 0.125ns 0.125ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "h_cntrl\[1\] ce int_ce 5.974 ns register " "Info: tco from clock \"h_cntrl\[1\]\" to destination pin \"ce\" through register \"int_ce\" is 5.974 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "h_cntrl\[1\] source 3.340 ns + Longest register " "Info: + Longest clock path from clock \"h_cntrl\[1\]\" to source register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns h_cntrl\[1\] 1 CLK PIN_14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { h_cntrl[1] } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.724 ns) + CELL(0.319 ns) 2.770 ns decod6 2 COMB LC_X5_Y1_N9 1 " "Info: 2: + IC(1.724 ns) + CELL(0.319 ns) = 2.770 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'decod6'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { h_cntrl[1] decod6 } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.125 ns) 3.340 ns int_ce 3 REG LC_X5_Y1_N0 1 " "Info: 3: + IC(0.445 ns) + CELL(0.125 ns) = 3.340 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { decod6 int_ce } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.171 ns ( 35.06 % ) " "Info: Total cell delay = 1.171 ns ( 35.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.169 ns ( 64.94 % ) " "Info: Total interconnect delay = 2.169 ns ( 64.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.340 ns" { h_cntrl[1] decod6 int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.340 ns" { h_cntrl[1] {} h_cntrl[1]~combout {} decod6 {} int_ce {} } { 0.000ns 0.000ns 1.724ns 0.445ns } { 0.000ns 0.727ns 0.319ns 0.125ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.634 ns + Longest register pin " "Info: + Longest register to pin delay is 2.634 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_ce 1 REG LC_X5_Y1_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_ce } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(1.454 ns) 2.634 ns ce 2 PIN PIN_52 0 " "Info: 2: + IC(1.180 ns) + CELL(1.454 ns) = 2.634 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'ce'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.634 ns" { int_ce ce } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 55.20 % ) " "Info: Total cell delay = 1.454 ns ( 55.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.180 ns ( 44.80 % ) " "Info: Total interconnect delay = 1.180 ns ( 44.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.634 ns" { int_ce ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.634 ns" { int_ce {} ce {} } { 0.000ns 1.180ns } { 0.000ns 1.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.340 ns" { h_cntrl[1] decod6 int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.340 ns" { h_cntrl[1] {} h_cntrl[1]~combout {} decod6 {} int_ce {} } { 0.000ns 0.000ns 1.724ns 0.445ns } { 0.000ns 0.727ns 0.319ns 0.125ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.634 ns" { int_ce ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.634 ns" { int_ce {} ce {} } { 0.000ns 1.180ns } { 0.000ns 1.454ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "h_cntrl\[1\] re 5.515 ns Longest " "Info: Longest tpd from source pin \"h_cntrl\[1\]\" to destination pin \"re\" is 5.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns h_cntrl\[1\] 1 CLK PIN_14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { h_cntrl[1] } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.571 ns) 2.974 ns re~21 2 COMB LC_X5_Y1_N4 1 " "Info: 2: + IC(1.676 ns) + CELL(0.571 ns) = 2.974 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; COMB Node = 're~21'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.247 ns" { h_cntrl[1] re~21 } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(1.454 ns) 5.515 ns re 3 PIN PIN_53 0 " "Info: 3: + IC(1.087 ns) + CELL(1.454 ns) = 5.515 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 're'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.541 ns" { re~21 re } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.752 ns ( 49.90 % ) " "Info: Total cell delay = 2.752 ns ( 49.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.763 ns ( 50.10 % ) " "Info: Total interconnect delay = 2.763 ns ( 50.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { h_cntrl[1] re~21 re } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "5.515 ns" { h_cntrl[1] {} h_cntrl[1]~combout {} re~21 {} re {} } { 0.000ns 0.000ns 1.676ns 1.087ns } { 0.000ns 0.727ns 0.571ns 1.454ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "int_ce e_d h_cntrl\[1\] 0.859 ns register " "Info: th for register \"int_ce\" (data pin = \"e_d\", clock pin = \"h_cntrl\[1\]\") is 0.859 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "h_cntrl\[1\] destination 3.340 ns + Longest register " "Info: + Longest clock path from clock \"h_cntrl\[1\]\" to destination register is 3.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns h_cntrl\[1\] 1 CLK PIN_14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { h_cntrl[1] } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.724 ns) + CELL(0.319 ns) 2.770 ns decod6 2 COMB LC_X5_Y1_N9 1 " "Info: 2: + IC(1.724 ns) + CELL(0.319 ns) = 2.770 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'decod6'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { h_cntrl[1] decod6 } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.125 ns) 3.340 ns int_ce 3 REG LC_X5_Y1_N0 1 " "Info: 3: + IC(0.445 ns) + CELL(0.125 ns) = 3.340 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { decod6 int_ce } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.171 ns ( 35.06 % ) " "Info: Total cell delay = 1.171 ns ( 35.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.169 ns ( 64.94 % ) " "Info: Total interconnect delay = 2.169 ns ( 64.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.340 ns" { h_cntrl[1] decod6 int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.340 ns" { h_cntrl[1] {} h_cntrl[1]~combout {} decod6 {} int_ce {} } { 0.000ns 0.000ns 1.724ns 0.445ns } { 0.000ns 0.727ns 0.319ns 0.125ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.481 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns e_d 1 PIN PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_43; Fanout = 4; PIN Node = 'e_d'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { e_d } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.462 ns) 2.481 ns int_ce 2 REG LC_X5_Y1_N0 1 " "Info: 2: + IC(1.311 ns) + CELL(0.462 ns) = 2.481 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.773 ns" { e_d int_ce } "NODE_NAME" } } { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.170 ns ( 47.16 % ) " "Info: Total cell delay = 1.170 ns ( 47.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.311 ns ( 52.84 % ) " "Info: Total interconnect delay = 1.311 ns ( 52.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { e_d int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { e_d {} e_d~combout {} int_ce {} } { 0.000ns 0.000ns 1.311ns } { 0.000ns 0.708ns 0.462ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "3.340 ns" { h_cntrl[1] decod6 int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "3.340 ns" { h_cntrl[1] {} h_cntrl[1]~combout {} decod6 {} int_ce {} } { 0.000ns 0.000ns 1.724ns 0.445ns } { 0.000ns 0.727ns 0.319ns 0.125ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { e_d int_ce } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { e_d {} e_d~combout {} int_ce {} } { 0.000ns 0.000ns 1.311ns } { 0.000ns 0.708ns 0.462ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 7 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 15 16:37:09 2007 " "Info: Processing ended: Thu Nov 15 16:37:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Info: Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}