prev_cmp_nand_interface.qmsg

利用MAX II CPLD 实现 NAND 闪存接口

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 15 16:36:56 2007 " "Info: Processing started: Thu Nov 15 16:36:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off nand_interface -c nand_interface " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nand_interface -c nand_interface" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nand_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file nand_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 nand_interface " "Info: Found entity 1: nand_interface" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "nand_interface " "Info: Elaborating entity \"nand_interface\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "decod7 nand_interface.v(42) " "Warning (10036): Verilog HDL or VHDL warning at nand_interface.v(42): object \"decod7\" assigned a value but never read" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_ale nand_interface.v(67) " "Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(67): inferring latch(es) for variable \"int_ale\", which holds its previous value in one or more paths through the always construct" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_se nand_interface.v(79) " "Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(79): inferring latch(es) for variable \"int_se\", which holds its previous value in one or more paths through the always construct" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 79 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_wp nand_interface.v(91) " "Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(91): inferring latch(es) for variable \"int_wp\", which holds its previous value in one or more paths through the always construct" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 91 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "int_ce nand_interface.v(103) " "Warning (10240): Verilog HDL Always Construct warning at nand_interface.v(103): inferring latch(es) for variable \"int_ce\", which holds its previous value in one or more paths through the always construct" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_ce nand_interface.v(103) " "Info (10041): Inferred latch for \"int_ce\" at nand_interface.v(103)" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 103 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_wp nand_interface.v(91) " "Info (10041): Inferred latch for \"int_wp\" at nand_interface.v(91)" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 91 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_se nand_interface.v(79) " "Info (10041): Inferred latch for \"int_se\" at nand_interface.v(79)" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 79 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "int_ale nand_interface.v(67) " "Info (10041): Inferred latch for \"int_ale\" at nand_interface.v(67)" {  } { { "nand_interface.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN500/quartus/nand_interface.v" 67 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}