nand_interface.tan.rpt

利用MAX II CPLD 实现 NAND 闪存接口

+-------+--------------+------------+---------+-----+------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+------------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To  ;
+-------+-------------------+-----------------+------------+-----+
; N/A   ; None              ; 5.515 ns        ; h_cntrl[1] ; re  ;
; N/A   ; None              ; 5.341 ns        ; h_cntrl[2] ; cle ;
; N/A   ; None              ; 5.253 ns        ; h_cntrl[0] ; re  ;
; N/A   ; None              ; 5.181 ns        ; h_cntrl[1] ; cle ;
; N/A   ; None              ; 4.848 ns        ; h_cntrl[2] ; re  ;
; N/A   ; None              ; 4.828 ns        ; h_rd_wr    ; re  ;
; N/A   ; None              ; 4.827 ns        ; h_cntrl[0] ; cle ;
; N/A   ; None              ; 4.603 ns        ; h_cntrl[1] ; we  ;
; N/A   ; None              ; 4.462 ns        ; h_rd_wr    ; we  ;
; N/A   ; None              ; 4.352 ns        ; h_cntrl[2] ; we  ;
; N/A   ; None              ; 4.211 ns        ; h_cntrl[0] ; we  ;
+-------+-------------------+-----------------+------------+-----+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+---------+------------+
; Minimum Slack ; Required th ; Actual th ; From ; To      ; To Clock   ;
+---------------+-------------+-----------+------+---------+------------+
; N/A           ; None        ; 0.859 ns  ; e_d  ; int_ce  ; h_cntrl[1] ;
; N/A           ; None        ; 0.851 ns  ; e_d  ; int_wp  ; h_cntrl[1] ;
; N/A           ; None        ; 0.604 ns  ; e_d  ; int_se  ; h_cntrl[1] ;
; N/A           ; None        ; 0.600 ns  ; e_d  ; int_ale ; h_cntrl[1] ;
; N/A           ; None        ; 0.550 ns  ; e_d  ; int_ce  ; h_cntrl[2] ;
; N/A           ; None        ; 0.542 ns  ; e_d  ; int_wp  ; h_cntrl[2] ;
; N/A           ; None        ; 0.466 ns  ; e_d  ; int_ce  ; h_cntrl[0] ;
; N/A           ; None        ; 0.458 ns  ; e_d  ; int_wp  ; h_cntrl[0] ;
; N/A           ; None        ; 0.295 ns  ; e_d  ; int_se  ; h_cntrl[2] ;
; N/A           ; None        ; 0.293 ns  ; e_d  ; int_ale ; h_cntrl[2] ;
; N/A           ; None        ; 0.212 ns  ; e_d  ; int_se  ; h_cntrl[0] ;
; N/A           ; None        ; 0.203 ns  ; e_d  ; int_ale ; h_cntrl[0] ;
+---------------+-------------+-----------+------+---------+------------+


+----------------------------------------------------------------+
; Timing Analyzer INI Usage                                      ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:56:28 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off nand_interface -c nand_interface
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "int_ce" is a latch
    Warning: Node "int_ale" is a latch
    Warning: Node "int_se" is a latch
    Warning: Node "int_wp" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "h_cntrl[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "h_cntrl[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "h_cntrl[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "decod5~21" as buffer
    Info: Detected gated clock "decod4~29" as buffer
    Info: Detected gated clock "decod3~9" as buffer
    Info: Detected gated clock "decod6" as buffer
Info: tsu for register "int_ale" (data pin = "e_d", clock pin = "h_cntrl[0]") is 1.470 ns
    Info: + Longest pin to register delay is 2.480 ns
        Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_43; Fanout = 4; PIN Node = 'e_d'
        Info: 2: + IC(1.310 ns) + CELL(0.462 ns) = 2.480 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'int_ale'
        Info: Total cell delay = 1.170 ns ( 47.18 % )
        Info: Total interconnect delay = 1.310 ns ( 52.82 % )
    Info: + Micro setup delay of destination is 1.673 ns
    Info: - Shortest clock path from clock "h_cntrl[0]" to destination register is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_89; Fanout = 7; CLK Node = 'h_cntrl[0]'
        Info: 2: + IC(1.534 ns) + CELL(0.125 ns) = 2.367 ns; Loc. = LC_X5_Y1_N1; Fanout = 1; COMB Node = 'decod3~9'
        Info: 3: + IC(0.191 ns) + CELL(0.125 ns) = 2.683 ns; Loc. = LC_X5_Y1_N2; Fanout = 1; REG Node = 'int_ale'
        Info: Total cell delay = 0.958 ns ( 35.71 % )
        Info: Total interconnect delay = 1.725 ns ( 64.29 % )
Info: tco from clock "h_cntrl[1]" to destination pin "ce" through register "int_ce" is 5.974 ns
    Info: + Longest clock path from clock "h_cntrl[1]" to source register is 3.340 ns
        Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl[1]'
        Info: 2: + IC(1.724 ns) + CELL(0.319 ns) = 2.770 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'decod6'
        Info: 3: + IC(0.445 ns) + CELL(0.125 ns) = 3.340 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'
        Info: Total cell delay = 1.171 ns ( 35.06 % )
        Info: Total interconnect delay = 2.169 ns ( 64.94 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 2.634 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'
        Info: 2: + IC(1.180 ns) + CELL(1.454 ns) = 2.634 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'ce'
        Info: Total cell delay = 1.454 ns ( 55.20 % )
        Info: Total interconnect delay = 1.180 ns ( 44.80 % )
Info: Longest tpd from source pin "h_cntrl[1]" to destination pin "re" is 5.515 ns
    Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl[1]'
    Info: 2: + IC(1.676 ns) + CELL(0.571 ns) = 2.974 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; COMB Node = 're~21'
    Info: 3: + IC(1.087 ns) + CELL(1.454 ns) = 5.515 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 're'
    Info: Total cell delay = 2.752 ns ( 49.90 % )
    Info: Total interconnect delay = 2.763 ns ( 50.10 % )
Info: th for register "int_ce" (data pin = "e_d", clock pin = "h_cntrl[1]") is 0.859 ns
    Info: + Longest clock path from clock "h_cntrl[1]" to destination register is 3.340 ns
        Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 7; CLK Node = 'h_cntrl[1]'
        Info: 2: + IC(1.724 ns) + CELL(0.319 ns) = 2.770 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'decod6'
        Info: 3: + IC(0.445 ns) + CELL(0.125 ns) = 3.340 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'
        Info: Total cell delay = 1.171 ns ( 35.06 % )
        Info: Total interconnect delay = 2.169 ns ( 64.94 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 2.481 ns
        Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_43; Fanout = 4; PIN Node = 'e_d'
        Info: 2: + IC(1.311 ns) + CELL(0.462 ns) = 2.481 ns; Loc. = LC_X5_Y1_N0; Fanout = 1; REG Node = 'int_ce'
        Info: Total cell delay = 1.170 ns ( 47.16 % )
        Info: Total interconnect delay = 1.311 ns ( 52.84 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 7 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Thu Nov 22 16:56:31 2007
    Info: Elapsed time: 00:00:03