📄 ioat91sam9263.h
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AT91_REG SYS_PIOD_MDSR; // Multi-driver Status Register
AT91_REG Reserved40[1]; //
AT91_REG SYS_PIOD_PPUDR; // Pull-up Disable Register
AT91_REG SYS_PIOD_PPUER; // Pull-up Enable Register
AT91_REG SYS_PIOD_PPUSR; // Pull-up Status Register
AT91_REG Reserved41[1]; //
AT91_REG SYS_PIOD_ASR; // Select A Register
AT91_REG SYS_PIOD_BSR; // Select B Register
AT91_REG SYS_PIOD_ABSR; // AB Select Status Register
AT91_REG Reserved42[9]; //
AT91_REG SYS_PIOD_OWER; // Output Write Enable Register
AT91_REG SYS_PIOD_OWDR; // Output Write Disable Register
AT91_REG SYS_PIOD_OWSR; // Output Write Status Register
AT91_REG Reserved43[85]; //
AT91_REG SYS_PIOE_PER; // PIO Enable Register
AT91_REG SYS_PIOE_PDR; // PIO Disable Register
AT91_REG SYS_PIOE_PSR; // PIO Status Register
AT91_REG Reserved44[1]; //
AT91_REG SYS_PIOE_OER; // Output Enable Register
AT91_REG SYS_PIOE_ODR; // Output Disable Registerr
AT91_REG SYS_PIOE_OSR; // Output Status Register
AT91_REG Reserved45[1]; //
AT91_REG SYS_PIOE_IFER; // Input Filter Enable Register
AT91_REG SYS_PIOE_IFDR; // Input Filter Disable Register
AT91_REG SYS_PIOE_IFSR; // Input Filter Status Register
AT91_REG Reserved46[1]; //
AT91_REG SYS_PIOE_SODR; // Set Output Data Register
AT91_REG SYS_PIOE_CODR; // Clear Output Data Register
AT91_REG SYS_PIOE_ODSR; // Output Data Status Register
AT91_REG SYS_PIOE_PDSR; // Pin Data Status Register
AT91_REG SYS_PIOE_IER; // Interrupt Enable Register
AT91_REG SYS_PIOE_IDR; // Interrupt Disable Register
AT91_REG SYS_PIOE_IMR; // Interrupt Mask Register
AT91_REG SYS_PIOE_ISR; // Interrupt Status Register
AT91_REG SYS_PIOE_MDER; // Multi-driver Enable Register
AT91_REG SYS_PIOE_MDDR; // Multi-driver Disable Register
AT91_REG SYS_PIOE_MDSR; // Multi-driver Status Register
AT91_REG Reserved47[1]; //
AT91_REG SYS_PIOE_PPUDR; // Pull-up Disable Register
AT91_REG SYS_PIOE_PPUER; // Pull-up Enable Register
AT91_REG SYS_PIOE_PPUSR; // Pull-up Status Register
AT91_REG Reserved48[1]; //
AT91_REG SYS_PIOE_ASR; // Select A Register
AT91_REG SYS_PIOE_BSR; // Select B Register
AT91_REG SYS_PIOE_ABSR; // AB Select Status Register
AT91_REG Reserved49[9]; //
AT91_REG SYS_PIOE_OWER; // Output Write Enable Register
AT91_REG SYS_PIOE_OWDR; // Output Write Disable Register
AT91_REG SYS_PIOE_OWSR; // Output Write Status Register
AT91_REG Reserved50[85]; //
AT91_REG SYS_PMC_SCER; // System Clock Enable Register
AT91_REG SYS_PMC_SCDR; // System Clock Disable Register
AT91_REG SYS_PMC_SCSR; // System Clock Status Register
AT91_REG Reserved51[1]; //
AT91_REG SYS_PMC_PCER; // Peripheral Clock Enable Register
AT91_REG SYS_PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG SYS_PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved52[1]; //
AT91_REG SYS_PMC_MOR; // Main Oscillator Register
AT91_REG SYS_PMC_MCFR; // Main Clock Frequency Register
AT91_REG SYS_PMC_PLLAR; // PLL A Register
AT91_REG SYS_PMC_PLLBR; // PLL B Register
AT91_REG SYS_PMC_MCKR; // Master Clock Register
AT91_REG Reserved53[3]; //
AT91_REG SYS_PMC_PCKR[8]; // Programmable Clock Register
AT91_REG SYS_PMC_IER; // Interrupt Enable Register
AT91_REG SYS_PMC_IDR; // Interrupt Disable Register
AT91_REG SYS_PMC_SR; // Status Register
AT91_REG SYS_PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved54[36]; //
AT91_REG SYS_RSTC_RCR; // Reset Control Register
AT91_REG SYS_RSTC_RSR; // Reset Status Register
AT91_REG SYS_RSTC_RMR; // Reset Mode Register
AT91_REG Reserved55[1]; //
AT91_REG SYS_SHDWC_SHCR; // Shut Down Control Register
AT91_REG SYS_SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SYS_SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved56[1]; //
AT91_REG SYS_RTTC0_RTMR; // Real-time Mode Register
AT91_REG SYS_RTTC0_RTAR; // Real-time Alarm Register
AT91_REG SYS_RTTC0_RTVR; // Real-time Value Register
AT91_REG SYS_RTTC0_RTSR; // Real-time Status Register
AT91_REG SYS_PITC_PIMR; // Period Interval Mode Register
AT91_REG SYS_PITC_PISR; // Period Interval Status Register
AT91_REG SYS_PITC_PIVR; // Period Interval Value Register
AT91_REG SYS_PITC_PIIR; // Period Interval Image Register
AT91_REG SYS_WDTC_WDCR; // Watchdog Control Register
AT91_REG SYS_WDTC_WDMR; // Watchdog Mode Register
AT91_REG SYS_WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved57[1]; //
AT91_REG SYS_RTTC1_RTMR; // Real-time Mode Register
AT91_REG SYS_RTTC1_RTAR; // Real-time Alarm Register
AT91_REG SYS_RTTC1_RTVR; // Real-time Value Register
AT91_REG SYS_RTTC1_RTSR; // Real-time Status Register
AT91_REG SYS_GPBR[20]; // General Purpose Register
} AT91S_SYS, *AT91PS_SYS;
#else
#define ECC0 (AT91_CAST(AT91_REG *) 0x00000000) // (ECC0) ECC 0
#define ECC1 (AT91_CAST(AT91_REG *) 0x00000600) // (ECC1) ECC 0
#define GPBR (AT91_CAST(AT91_REG *) 0x00001D60) // (GPBR) General Purpose Register
#endif
// -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface 0
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_EBI0 {
AT91_REG EBI0_DUMMY; // Dummy register - Do not use
} AT91S_EBI0, *AT91PS_EBI0;
#else
#define EBI0_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI0_DUMMY) Dummy register - Do not use
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
#else
#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
#endif
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
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