at91sam9263_sdram.mac

ucOS_9263_Source ucOS-ii for 9263 port,from Micrium.com

// ---------------------------------------------------------
//   ATMEL Microcontroller Software Support  -  ROUSSET  -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any  kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
//  File: SAM9_SDRAM.mac
//  User setup file for CSPY debugger.
//  1.1 08/Aug/06 jpp    : Creation
//
//  $Revision: 1.1 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;

/*********************************************************************
*
*       execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
    __hw_reset(0);
    __message "------------------------------ execUserReset ---------------------------------";
    CheckNoRemap();
    ini();
    __PllSetting100MHz();
    __AIC();                                                    //* Init AIC
    __message "-------------------------------Set PC Reset ----------------------------------";
    __writeMemory32(0xD3,0x98,"Register");                      //*  Set CPSR
    __writeMemory32(0x20000000,0xB4,"Register");                //*  Set PC (R15)
}

/*********************************************************************
*
*       execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
    __message "------------------------------ execUserPreload ---------------------------------";
    __writeMemory32(0xD3,0x98,"Register");                      //*  Set CPSR
    __PllSetting();                                             //* Init PLL
    __PllSetting100MHz();
    __initSDRAM();                                              //* Init SDRAM before load
    __AIC();                                                    //* Init AIC
    CheckNoRemap();                                             //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
    Watchdog();                                                 //* Watchdog Disable

                                                                //*  Get the Chip ID  (AT91C_DBGU_C1R & AT91C_DBGU_C2R
    __mac_i=__readMemory32(0xFFFFF240,"Memory");
    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;
}

/*********************************************************************
*
*       __initSDRAM()
* Function description
* Set SDRAM for works at 100 MHz
**********************************************************************/

__initSDRAM()
{
    __var  PIOD_ASR;      PIOD_ASR     = 0xFFFFF870;
    __var  PIOD_BSR;      PIOD_BSR     = 0xFFFFF874;
    __var  PIOD_PDR;      PIOD_PDR     = 0xFFFFF804;

    __var  CCFG_EBI0CSA;  CCFG_EBI0CSA = 0xFFFFED20;

    __var  SDRAMC0_MR;    SDRAMC0_MR   = 0xFFFFE200;
    __var  SDRAMC0_TR;    SDRAMC0_TR   = 0xFFFFE204;
    __var  SDRAMC0_CR;    SDRAMC0_CR   = 0xFFFFE208;
    __var  SDRAMC0_HSR;   SDRAMC0_HSR  = 0xFFFFE20C;
    __var  SDRAMC0_LPR;   SDRAMC0_LPR  = 0xFFFFE200;
    __var  SDRAMC0_IER;   SDRAMC0_IER  = 0xFFFFE200;
    __var  SDRAMC0_IDR;   SDRAMC0_IDR  = 0xFFFFE200;
    __var  SDRAMC0_IMR;   SDRAMC0_IMR  = 0xFFFFE200;
    __var  SDRAMC0_ISR;   SDRAMC0_ISR  = 0xFFFFE200;
    __var  SDRAMC0_MDR;   SDRAMC0_MDR  = 0xFFFFE200;

    __var  i;

                                                                /* --------------- CONFIGURE MATRIX --------------- */
    __writeMemory32(0x00010002, CCFG_EBI0CSA, "Memory");        /* SDRAM on EBI0 CS1                                */

                                                                /* ----------------- CONFIGURE PIO ---------------- */
    __writeMemory32(0xFFFF0000, PIOD_ASR,     "Memory");        /* Select peripheral function A for PD16:31         */
    __writeMemory32(0x00000000, PIOD_BSR,     "Memory");        /* Select peripheral function B for no pins         */
    __writeMemory32(0xFFFF0000, PIOD_PDR,     "Memory");        /* Disable PIO for PD16:31                          */


                                                                /* ---------------- CONFIGURE SDRAMC -------------- */
    __writeMemory32(0x0008EF5A, SDRAMC0_TR,   "Memory");
    __writeMemory32(0x85227279, SDRAMC0_CR,   "Memory");        /* Set SDRAM timings:                               */
                                                                /*    NC_9              NR_13                       */
                                                                /*    CAS_3             NB_4_BANKS                  */
                                                                /*    DBW_32_BITS       TWR_2                       */
                                                                /*    TRC_7             TRP_2                       */
                                                                /*    TRCD_2            TRAS_5                      */
                                                                /*    TXSR_8                                        */

    __sleep(100);

    __writeMemory32(0x00000002, SDRAMC0_MR,   "Memory");        /* Set precharge all                                */
    __writeMemory32(0x00000000, 0x20000000,   "Memory");        /* Perform precharge                                */

    __sleep(100);

    __writeMemory32(0x00000004, SDRAMC0_MR,   "Memory");        /* Set first CBR                                    */

                                                                /* Perform 8 refresh cycles                         */
    for(i = 1; i <= 8; i++) {
        __writeMemory32(i, (0x20000000 + (i * 16)), "Memory");
    }

    __writeMemory32(0x00000003, SDRAMC0_MR,   "Memory");        /* Set LMR operation                                */
    __writeMemory32(0xCAFEDEDE, 0x20000090,   "Memory");        /* Perform LMR                                      */
    __writeMemory32(0x000002EE, SDRAMC0_TR,   "Memory");        /* Set refresh timer                                */
    __writeMemory32(0x00000000, SDRAMC0_MR,   "Memory");        /* Set normal mode                                  */
    __writeMemory32(0x00000000, 0x20000000,   "Memory");        /* Perform normal mode                              */

    __message "------------------------------------- SDRAM Done at 100 MHz -----------------------------------------";
}

/*********************************************************************
*
*       __PllSetting()
* Function description
*   Initializes the PMC.
*   1. Enable the Main Oscillator
*   2. Configure PLL
*   3. Switch Master
*/
__PllSetting()
{
     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//*    pPmc->PMC_IDR = 0xFFFFFFFF;
    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");

// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
    __sleep(10000);

// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");

// AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
    __sleep(10000);
    __emulatorSpeed(0);               //* Set JTAG speed to full speed

   __message "------------------------------- PLL  Enable -----------------------------------------";
   } else {
   __message " ********* Core in SLOW CLOCK mode ********* "; }
}


/*********************************************************************
*
*       __PllSetting100MHz()
* Function description
*   Set core at 200 MHz and MCK at 100 MHz