📄 bsp.c
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cpu_freq = BSP_CPU_ClkFreq();
mclk_div = (AT91C_BASE_PMC->PMC_MCKR >> 8) & 0x03; /* Read the Master Clock divider */
mclk_div = 1 << mclk_div; /* Convert 0-3 into 1, 2, 4 */
cpu_freq = cpu_freq / mclk_div;
return (cpu_freq);
}
/*
*********************************************************************************************************
* EXCEPTION HANDLER
*
* Description : This function should be used to handle any exceptions. It is called by
* OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in os_cpu_a.s
*
* Arguments : ID, an identifier used to indicate what type of ARM exception has been triggered
* Possible ID values are shown below.
* OS_CPU_ARM_EXCEPT_RESET 0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR 0x01
* OS_CPU_ARM_EXCEPT_SWI 0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT 0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT 0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT 0x05
* OS_CPU_ARM_EXCEPT_IRQ 0x06
* OS_CPU_ARM_EXCEPT_FIQ 0x07
*********************************************************************************************************
*/
void OS_CPU_ExceptHndlr (CPU_INT32U except_id)
{
BSP_FNCT_PTR pfnct;
CPU_INT32U *sp;
if (except_id == OS_CPU_ARM_EXCEPT_IRQ) {
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_IVR; /* Read the interrupt vector from the VIC */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer */
(*pfnct)(); /* Execute the ISR for the interrupting device */
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
pfnct = (BSP_FNCT_PTR)(AT91C_BASE_AIC->AIC_IVR); /* Read IRQ hanlder from the AIC */
}
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
} else if (except_id == OS_CPU_ARM_EXCEPT_FIQ) {
pfnct = (BSP_FNCT_PTR)AT91C_BASE_AIC->AIC_FVR; /* Read the interrupt vector from the VIC */
while (pfnct != (BSP_FNCT_PTR)0) { /* Make sure we don't have a NULL pointer */
(*pfnct)(); /* Execute the ISR for the interrupting device */
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
pfnct = (BSP_FNCT_PTR)(AT91C_BASE_AIC->AIC_FVR); /* Read FIQ handler from the AIC */
}
AT91C_BASE_AIC->AIC_EOICR = 0; /* End of handler */
} else {
sp = (CPU_INT32U *)OSTCBCur->OSTCBStkPtr;
APP_TRACE_INFO(("\nCPU_ARM_EXCEPTION #%d trapped.\n", except_id));
APP_TRACE_INFO(("R0 : 0x%08x\n", *(sp + 0x01)));
APP_TRACE_INFO(("R1 : 0x%08x\n", *(sp + 0x02)));
APP_TRACE_INFO(("R2 : 0x%08x\n", *(sp + 0x03)));
APP_TRACE_INFO(("R3 : 0x%08x\n", *(sp + 0x04)));
APP_TRACE_INFO(("R4 : 0x%08x\n", *(sp + 0x05)));
APP_TRACE_INFO(("R5 : 0x%08x\n", *(sp + 0x06)));
APP_TRACE_INFO(("R6 : 0x%08x\n", *(sp + 0x07)));
APP_TRACE_INFO(("R7 : 0x%08x\n", *(sp + 0x08)));
APP_TRACE_INFO(("R8 : 0x%08x\n", *(sp + 0x09)));
APP_TRACE_INFO(("R9 : 0x%08x\n", *(sp + 0x0A)));
APP_TRACE_INFO(("R10 : 0x%08x\n", *(sp + 0x0B)));
APP_TRACE_INFO(("R11 : 0x%08x\n", *(sp + 0x0C)));
APP_TRACE_INFO(("R12 : 0x%08x\n", *(sp + 0x0D)));
APP_TRACE_INFO(("SP : 0x%08x\n", sp));
APP_TRACE_INFO(("LR : 0x%08x\n", *(sp + 0x0E)));
APP_TRACE_INFO(("PC : 0x%08x\n", *(sp + 0x0F)));
APP_TRACE_INFO(("CPSR: 0x%08x\n", *(sp + 0x00)));
/* Infinite loop on other exceptions. */
/* Should be replaced by other behavior (reboot, etc.) */
while (DEF_TRUE) {
;
}
}
}
/*
*********************************************************************************************************
* DISABLE ALL INTERRUPTS
*
* Description : This function is called to disable ALL interrupts.
*
* Argument(s) : none
*
* Returns : none
*********************************************************************************************************
*/
void BSP_IntDisAll (void)
{
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; /* Disable all interrupts */
}
/*
******************************************************************************************************************************
******************************************************************************************************************************
** External Memory Initialization
******************************************************************************************************************************
******************************************************************************************************************************
*/
/*
*********************************************************************************************************
* SDRAM Initialization
*
* Description : This function initializes SDRAM operating parameters
*
* Argument(s) : none
*
* Returns : none
*********************************************************************************************************
*/
void SDRAM_Init (void)
{
CPU_INT32U *sdram;
CPU_INT32U i;
sdram = (CPU_INT32U *)0x20000000;
AT91C_BASE_CCFG->CCFG_EBI0CSA|= 0x00010002;
AT91C_BASE_PIOD->PIO_ASR = GPIOD_EBI0_D;
AT91C_BASE_PIOD->PIO_BSR = 0;
AT91C_BASE_PIOD->PIO_PDR = GPIOD_EBI0_D;
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SYS); /* Enable clocks for SDRAM */
/* SDRAM Configuration Register */
AT91C_BASE_SDRAMC0->SDRAMC_CR = AT91C_SDRAMC_TXSR_8 /* TXSR [31:28] = 8 Clock Cycles */
| AT91C_SDRAMC_TRAS_5 /* TRAS [27:24] = 5 Clock Cycles */
| AT91C_SDRAMC_TRCD_2 /* TRCD [23:20] = 2 Clock Cycles */
| AT91C_SDRAMC_TRP_2 /* TRP [19:16] = 2 Clock Cycles */
| AT91C_SDRAMC_TRC_7 /* TRC [15:12] = 7 Clock Cycles */
| AT91C_SDRAMC_TWR_2 /* TWR [11:08] = 2 Clock Cycles */
| AT91C_SDRAMC_DBW_32_BITS /* DBW [07:07] = 0 Clock Cycles */
| AT91C_SDRAMC_CAS_3 /* CAS [06:05] = 2 Clock Cycles */
| AT91C_SDRAMC_NB_4_BANKS /* NB [04:04] = 4 Banks */
| AT91C_SDRAMC_NR_13 /* NR [03:02] = 13 Rows Bits */
| AT91C_SDRAMC_NC_9; /* NC [01:00] = 9 Column Bits */
for (i = 0; i < 5000; i++) {
;
}
AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_PRCGALL_CMD; /* Issue All Banks Precharge command */
*sdram = 0x00000000; /* Perform write */
for (i = 0; i < 5000; i++) {
;
}
for (i = 1; i <= 8; i++) { /* Perform eight refresh cycles */
AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD;/* Issue CBR command */
*(sdram + 4 * i) = i; /* Perform write */
}
AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; /* Issue Mode Register set command */
*(sdram + 0x24) = 0xcafedede; /* Perform write */
AT91C_BASE_SDRAMC0->SDRAMC_TR = (7.81 * (CPU_FP32)BSP_CPU_MclkFreq() / 1000000.); /* SDRAM Refresh Time (7.81uS * MCLK)*/
/* where 7.81uS is the RAM tREF parameter */
AT91C_BASE_SDRAMC0->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; /* Enter normal mode */
*sdram = 0x00000000; /* Perform write */
}
/*
******************************************************************************************************************************
******************************************************************************************************************************
** PB, LED, and ADC Functions
******************************************************************************************************************************
******************************************************************************************************************************
*/
/*
*********************************************************************************************************
* LED INITIALIZATION
*
* Description : This function initializes the LED I/O pins.
*
* Argument(s) : none
*
* Returns : none
*********************************************************************************************************
*/
static void LED_Init (void)
{
/* ------------------------- LED1 ------------------------- */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE; /* Enable peripheral clock */
AT91C_BASE_PIOC->PIO_PER = GPIOC_PWM2; /* Enable register */
AT91C_BASE_PIOC->PIO_OER = GPIOC_PWM2; /* Output enable */
AT91C_BASE_PIOC->PIO_IDR = GPIOC_PWM2; /* Disable LED pin interrupt */
/* ------------------------- LED2 ------------------------- */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB; /* Enable peripheral clock */
AT91C_BASE_PIOB->PIO_PER = GPIOB_PWM1; /* Enable register */
AT91C_BASE_PIOB->PIO_OER = GPIOB_PWM1; /* Output enable */
AT91C_BASE_PIOB->PIO_IDR = GPIOB_PWM1; /* Disable LED pin interrupt */
/* -------------------- INITIALIZATION -------------------- */
LED_Off(0); /* Turn OFF all the LEDs */
}
/*
*********************************************************************************************************
* LED ON
*
* Description : This function is used turn on any or all of the LEDs on the board.
*
* Arguments : led is the number of the LED to control
* 0 indicates that you want ALL the LEDs to be ON
* 1 turns ON LED1 on the board
* 2 turns ON LED2 on the board
*
* Returns : none
*********************************************************************************************************
*/
void LED_On (CPU_INT08U led)
{
switch (led) {
case 0:
AT91C_BASE_PIOB->PIO_CODR = GPIOB_PWM1;
AT91C_BASE_PIOC->PIO_CODR = GPIOC_PWM2;
break;
case 1:
AT91C_BASE_PIOC->PIO_CODR = GPIOC_PWM2;
break;
case 2:
AT91C_BASE_PIOB->PIO_CODR = GPIOB_PWM1;
break;
default:
break;
}
}
/*
*********************************************************************************************************
* LED OFF
*
* Description : This function is used turn off any or all of the LEDs on the board.
*
* Arguments : led is the number of the LED to turn OFF
* 0 indicates that you want ALL the LEDs to be OFF
* 1 turns OFF LED1 on the board
* 2 turns OFF LED2 on the board
*
* Returns : none
*********************************************************************************************************
*/
void LED_Off (CPU_INT08U led)
{
switch (led) {
case 0:
AT91C_BASE_PIOB->PIO_SODR = GPIOB_PWM1;
AT91C_BASE_PIOC->PIO_SODR = GPIOC_PWM2;
break;
case 1:
AT91C_BASE_PIOC->PIO_SODR = GPIOC_PWM2;
break;
case 2:
AT91C_BASE_PIOB->PIO_SODR = GPIOB_PWM1;
break;
default:
break;
}
}
/*
*********************************************************************************************************
* LED TOGGLE
*
* Description : This function is used to toggle any or all the LEDs on the board.
*
* Arguments : led is the number of the LED to toggle
* 0 indicates that you want ALL the LEDs to be toggle
* 1 toggles LED1 on the board
* 2 toggles LED2 on the board
*
* Returns : none
*********************************************************************************************************
*/
void LED_Toggle (CPU_INT08U led)
{
switch (led) {
case 0:
if ((AT91C_BASE_PIOB->PIO_ODSR & GPIOB_PWM1) == GPIOB_PWM1) {
AT91C_BASE_PIOB->PIO_CODR = GPIOB_PWM1;
} else {
AT91C_BASE_PIOB->PIO_SODR = GPIOB_PWM1;
}
if ((AT91C_BASE_PIOC->PIO_ODSR & GPIOC_PWM2) == GPIOC_PWM2) {
AT91C_BASE_PIOC->PIO_CODR = GPIOC_PWM2;
} else {
AT91C_BASE_PIOC->PIO_SODR = GPIOC_PWM2;
}
break;
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