alu.qsf

ALU可以实现16种操作（包括加减乘除移位运算等）

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ALU_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:47:30  APRIL 17, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE reg.vhd
set_global_assignment -name VHDL_FILE ALU.vhd
set_global_assignment -name VHDL_FILE ../adder16/add4.vhd
set_global_assignment -name VHDL_FILE ../adder16/adder16.vhd
set_global_assignment -name VHDL_FILE ../sub16/sub16.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE ALU.vwf
set_global_assignment -name VHDL_FILE ../booth_multiplier/booth_multiplier.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_86 -to C
set_location_assignment PIN_29 -to clk
set_location_assignment PIN_200 -to Dinput[0]
set_location_assignment PIN_201 -to Dinput[1]
set_location_assignment PIN_202 -to Dinput[2]
set_location_assignment PIN_203 -to Dinput[3]
set_location_assignment PIN_214 -to Dinput[4]
set_location_assignment PIN_215 -to Dinput[5]
set_location_assignment PIN_216 -to Dinput[6]
set_location_assignment PIN_217 -to Dinput[7]
set_location_assignment PIN_223 -to Dinput[8]
set_location_assignment PIN_224 -to Dinput[9]
set_location_assignment PIN_225 -to Dinput[10]
set_location_assignment PIN_226 -to Dinput[11]
set_location_assignment PIN_234 -to Dinput[12]
set_location_assignment PIN_235 -to Dinput[13]
set_location_assignment PIN_236 -to Dinput[14]
set_location_assignment PIN_237 -to Dinput[15]
set_location_assignment PIN_12 -to OP[0]
set_location_assignment PIN_13 -to OP[1]
set_location_assignment PIN_14 -to OP[2]
set_location_assignment PIN_240 -to reset
set_location_assignment PIN_41 -to result[0]
set_location_assignment PIN_42 -to result[1]
set_location_assignment PIN_43 -to result[2]
set_location_assignment PIN_44 -to result[3]
set_location_assignment PIN_45 -to result[4]
set_location_assignment PIN_46 -to result[5]
set_location_assignment PIN_47 -to result[6]
set_location_assignment PIN_48 -to result[7]
set_location_assignment PIN_57 -to result[8]
set_location_assignment PIN_58 -to result[9]
set_location_assignment PIN_59 -to result[10]
set_location_assignment PIN_60 -to result[11]
set_location_assignment PIN_61 -to result[12]
set_location_assignment PIN_62 -to result[13]
set_location_assignment PIN_63 -to result[14]
set_location_assignment PIN_64 -to result[15]
set_location_assignment PIN_16 -to sel
set_location_assignment PIN_17 -to write
set_location_assignment PIN_85 -to Z
set_location_assignment PIN_15 -to OP[3]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Architect"
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY ALU

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C6
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name GLITCH_DETECTION OFF
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE OFF
set_global_assignment -name VECTOR_INPUT_SOURCE ALU.vwf

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_INPUT_GND_NAME GROUND -section_id eda_design_synthesis
	set_global_assignment -name EDA_LMF_FILE mnt8_bas.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------

# --------------------------------------------
# start EDA_TOOL_SETTINGS(eda_timing_analysis)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_timing_analysis
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis

# end EDA_TOOL_SETTINGS(eda_timing_analysis)
# ------------------------------------------