alu.fit.qmsg

来自「ALU可以实现16种操作（包括加减乘除移位运算等）」· QMSG 代码 · 共 40 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 03 20:33:00 2008 " "Info: Processing started: Sat May 03 20:33:00 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ALU -c ALU " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ALU -c ALU" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ALU EP1C6Q240C6 " "Info: Selected device EP1C6Q240C6 for design \"ALU\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C6 " "Info: Device EP1C12Q240C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 43 " "Info: No exact pin location assignment(s) for 1 pins of 43 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cin " "Info: Pin cin not assigned to an exact location on the device" {  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 14 -1 0 } } { "f:/quartus5.0/software/bin/Assignment Editor.qase" "" { Assignment "f:/quartus5.0/software/bin/Assignment Editor.qase" 1 { { 0 "cin" } } } } { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "" { cin } "NODE_NAME" } "" } } { "F:/Quartus5.0/cyzhangFile/ALU/ALU.fld" "" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/ALU.fld" "" "" { cin } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "C~10 " "Info: Destination \"C~10\" may be non-global or may not use global clock" {  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 16 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Z~262 " "Info: Destination \"Z~262\" may be non-global or may not use global clock" {  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 16 -1 0 } }  } 0}  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "reset " "Info: Pin \"reset\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 9 -1 0 } } { "f:/quartus5.0/software/bin/Assignment Editor.qase" "" { Assignment "f:/quartus5.0/software/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "" { reset } "NODE_NAME" } "" } } { "F:/Quartus5.0/cyzhangFile/ALU/ALU.fld" "" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/ALU.fld" "" "" { reset } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 1 0 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 21 23 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 21 total pin(s) used --  23 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 17 31 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 17 total pin(s) used --  31 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 6 42 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 6 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 8 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 8%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 20:33:06 2008 " "Info: Processing ended: Sat May 03 20:33:06 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}