alu.tan.qmsg

ALU可以实现16种操作（包括加减乘除移位运算等）

{ "Info" "ITDB_TH_RESULT" "reg:A_reg\|Q\[4\] Dinput\[4\] clk -3.419 ns register " "Info: th for register \"reg:A_reg\|Q\[4\]\" (data pin = \"Dinput\[4\]\", clock pin = \"clk\") is -3.419 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "" { clk } "NODE_NAME" } "" } } { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns reg:A_reg\|Q\[4\] 2 REG LC_X10_Y14_N1 33 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X10_Y14_N1; Fanout = 33; REG Node = 'reg:A_reg\|Q\[4\]'" {  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "1.141 ns" { clk reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/reg.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0}  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "2.271 ns" { clk reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 reg:A_reg|Q[4] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "reg.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/reg.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.702 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Dinput\[4\] 1 PIN PIN_214 2 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_214; Fanout = 2; PIN Node = 'Dinput\[4\]'" {  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "" { Dinput[4] } "NODE_NAME" } "" } } { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.478 ns) + CELL(0.089 ns) 5.702 ns reg:A_reg\|Q\[4\] 2 REG LC_X10_Y14_N1 33 " "Info: 2: + IC(4.478 ns) + CELL(0.089 ns) = 5.702 ns; Loc. = LC_X10_Y14_N1; Fanout = 33; REG Node = 'reg:A_reg\|Q\[4\]'" {  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "4.567 ns" { Dinput[4] reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/reg.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 21.47 % " "Info: Total cell delay = 1.224 ns ( 21.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.478 ns 78.53 % " "Info: Total interconnect delay = 4.478 ns ( 78.53 % )" {  } {  } 0}  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "5.702 ns" { Dinput[4] reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "5.702 ns" { Dinput[4] Dinput[4]~out0 reg:A_reg|Q[4] } { 0.000ns 0.000ns 4.478ns } { 0.000ns 1.135ns 0.089ns } } }  } 0}  } { { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "2.271 ns" { clk reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 reg:A_reg|Q[4] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } { "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" "" { Report "F:/Quartus5.0/cyzhangFile/ALU/db/ALU_cmp.qrpt" Compiler "ALU" "UNKNOWN" "V1" "F:/Quartus5.0/cyzhangFile/ALU/db/ALU.quartus_db" { Floorplan "F:/Quartus5.0/cyzhangFile/ALU/" "" "5.702 ns" { Dinput[4] reg:A_reg|Q[4] } "NODE_NAME" } "" } } { "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus5.0/software/bin/Technology_Viewer.qrui" "5.702 ns" { Dinput[4] Dinput[4]~out0 reg:A_reg|Q[4] } { 0.000ns 0.000ns 4.478ns } { 0.000ns 1.135ns 0.089ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 20:33:10 2008 " "Info: Processing ended: Sat May 03 20:33:10 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}