📄 alu.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 03 20:32:48 2008 " "Info: Processing started: Sat May 03 20:32:48 2008" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALU -c ALU " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ALU -c ALU" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg-behav " "Info: Found design unit 1: reg-behav" { } { { "reg.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/reg.vhd" 17 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg " "Info: Found entity 1: reg" { } { { "reg.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/reg.vhd" 4 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALU.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU-behav " "Info: Found design unit 1: ALU-behav" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 20 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 7 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adder16/add4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../adder16/add4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add4-behave " "Info: Found design unit 1: add4-behave" { } { { "../adder16/add4.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/adder16/add4.vhd" 15 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 add4 " "Info: Found entity 1: add4" { } { { "../adder16/add4.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/adder16/add4.vhd" 6 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adder16/adder16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../adder16/adder16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder16-behave " "Info: Found design unit 1: adder16-behave" { } { { "../adder16/adder16.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/adder16/adder16.vhd" 15 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder16 " "Info: Found entity 1: adder16" { } { { "../adder16/adder16.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/adder16/adder16.vhd" 6 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../sub16/sub16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../sub16/sub16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sub16-behave " "Info: Found design unit 1: sub16-behave" { } { { "../sub16/sub16.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/sub16/sub16.vhd" 15 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 sub16 " "Info: Found entity 1: sub16" { } { { "../sub16/sub16.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/sub16/sub16.vhd" 6 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../booth_multiplier/booth_multiplier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../booth_multiplier/booth_multiplier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 booth_multiplier-structural " "Info: Found design unit 1: booth_multiplier-structural" { } { { "../booth_multiplier/booth_multiplier.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/booth_multiplier/booth_multiplier.vhd" 15 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 booth_multiplier " "Info: Found entity 1: booth_multiplier" { } { { "../booth_multiplier/booth_multiplier.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/booth_multiplier/booth_multiplier.vhd" 5 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ALU " "Info: Elaborating entity \"ALU\" for the top level hierarchy" { } { } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "add_temp ALU.vhd(87) " "Warning: VHDL Process Statement warning at ALU.vhd(87): signal \"add_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 87 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C_tmp1 ALU.vhd(88) " "Warning: VHDL Process Statement warning at ALU.vhd(88): signal \"C_tmp1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 88 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sub_temp ALU.vhd(91) " "Warning: VHDL Process Statement warning at ALU.vhd(91): signal \"sub_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 91 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C_tmp2 ALU.vhd(92) " "Warning: VHDL Process Statement warning at ALU.vhd(92): signal \"C_tmp2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 92 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cin ALU.vhd(113) " "Warning: VHDL Process Statement warning at ALU.vhd(113): signal \"cin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 113 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cin ALU.vhd(115) " "Warning: VHDL Process Statement warning at ALU.vhd(115): signal \"cin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 115 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "result_t ALU.vhd(126) " "Warning: VHDL Process Statement warning at ALU.vhd(126): signal \"result_t\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 126 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "result_t ALU.vhd(82) " "Warning: VHDL Process Statement warning at ALU.vhd(82): signal or variable \"result_t\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"result_t\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 82 0 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg reg:A_reg " "Info: Elaborating entity \"reg\" for hierarchy \"reg:A_reg\"" { } { { "ALU.vhd" "A_reg" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 59 -1 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sub16 sub16:l2 " "Info: Elaborating entity \"sub16\" for hierarchy \"sub16:l2\"" { } { { "ALU.vhd" "l2" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 77 -1 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C_temp sub16.vhd(36) " "Warning: VHDL Process Statement warning at sub16.vhd(36): signal \"C_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "../sub16/sub16.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/sub16/sub16.vhd" 36 0 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder16 sub16:l2\|adder16:l1 " "Info: Elaborating entity \"adder16\" for hierarchy \"sub16:l2\|adder16:l1\"" { } { { "../sub16/sub16.vhd" "l1" { Text "F:/Quartus5.0/cyzhangFile/sub16/sub16.vhd" 28 -1 0 } } } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add4 sub16:l2\|adder16:l1\|add4:u1 " "Info: Elaborating entity \"add4\" for hierarchy \"sub16:l2\|adder16:l1\|add4:u1\"" { } { { "../adder16/adder16.vhd" "u1" { Text "F:/Quartus5.0/cyzhangFile/adder16/adder16.vhd" 28 -1 0 } } } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" { } { { "lpm_mult.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/lpm_mult.tdf" 274 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" { } { { "multcore.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/multcore.tdf" 175 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" { } { { "mpar_add.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/mpar_add.tdf" 60 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "lpm_add_sub.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "addcore.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "a_csnbuffer.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../software/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../software/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" { } { { "altshift.tdf" "" { Text "f:/quartus5.0/software/libraries/megafunctions/altshift.tdf" 28 1 0 } } } 0} } { } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "result_t\[16\] " "Warning: Latch result_t\[16\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA OP\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal OP\[2\]" { } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 10 -1 0 } } } 0} } { { "ALU.vhd" "" { Text "F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd" 55 -1 0 } } } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "593 " "Info: Implemented 593 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "25 " "Info: Implemented 25 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_LCELLS" "550 " "Info: Implemented 550 logic cells" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 03 20:32:58 2008 " "Info: Processing ended: Sat May 03 20:32:58 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" { } { } 0} } { } 0}
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