alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

SIGNAL l1_au3_ac2_a14_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ac2_a14_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_atemp2_a4_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_atemp2_a4_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a2_a_a115_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a2_a_a115_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10220_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10220_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a11_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au3_atemp0_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_atemp0_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_atemp2_a3_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_atemp2_a3_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_atemp3_a37_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_atemp3_a37_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_atemp1_a17_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_atemp1_a17_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a11_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a11_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10222_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10222_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1566_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1566_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1551_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1551_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1556_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1556_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10219_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10219_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10223_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10223_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10224_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10224_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a90_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a90_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a96_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a96_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a110_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a110_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a114_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a114_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10225_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10225_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10226_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10226_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10227_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10227_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a11_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a11_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10236_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10236_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a95_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a95_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a101_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a101_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a115_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a115_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a119_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a119_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10235_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10235_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1571_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1571_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1581_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1581_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1576_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1576_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10229_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10229_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_ac3_a24_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ac3_a24_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_atemp4_a58_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_atemp4_a58_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_ac3_a25_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ac3_a25_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a116_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a116_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_atemp5_a6_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_atemp5_a6_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_asum_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_asum_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10230_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10230_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a12_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a118_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a118_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a117_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a3_a_a117_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a12_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a12_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10232_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10232_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1586_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1586_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10233_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10233_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10234_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10234_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10237_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10237_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a12_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a12_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1601_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1601_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_ap_a72_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_ap_a72_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_ap_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_ap_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_ag_a221_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_ag_a221_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_ag_a222_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_ag_a222_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_ac12_a106_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_ac12_a106_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_acout_a189_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_acout_a189_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au4_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au4_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a13_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l1_au3_ag_a102_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ag_a102_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_ag_a101_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ag_a101_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_ag_a100_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ag_a100_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_ac12_a52_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_ac12_a52_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a43_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a43_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_ac12_a1_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_ac12_a1_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_ac12_a53_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_ac12_a53_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au4_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au4_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10240_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10240_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a13_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a13_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10242_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10242_