alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

SIGNAL l2_al1_au2_asum_a3_a_a129_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a3_a_a129_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10190_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10190_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a8_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a8_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1501_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1501_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1496_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1496_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10189_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10189_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10192_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10192_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1491_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1491_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10193_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10193_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10194_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10194_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10196_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10196_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10197_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10197_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a96_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a96_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a100_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a100_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a80_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a80_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a104_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a104_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10205_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10205_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a8_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a8_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1516_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1516_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1511_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1511_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10199_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10199_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a1_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a1_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ap_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ap_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a228_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a228_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a229_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ag_a229_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_ac8_a25_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_ac8_a25_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a9_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_ag_a177_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_ag_a177_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_ag_a178_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_ag_a178_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_ac8_a24_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_ac8_a24_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10200_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10200_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a9_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a9_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1521_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1521_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10202_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10202_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1526_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1526_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10203_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10203_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10204_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10204_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10206_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10206_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10207_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10207_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a9_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a9_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1546_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1546_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_ac1_a8_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_ac1_a8_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au3_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au3_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10210_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10210_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a10_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a1_a_a114_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a1_a_a114_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au3_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a10_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a10_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1536_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1536_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1541_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1541_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10209_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10209_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10212_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10212_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1531_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1531_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10213_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10213_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10214_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10214_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a101_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a101_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a105_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a105_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a85_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a85_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a109_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a109_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10215_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10215_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10216_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10216_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10217_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10217_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a10_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a10_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1561_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1561_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_ac8_a1_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_ac8_a1_I_pathsel : std_logic_vector(10 DOWNTO 0);