alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

SIGNAL l1_au2_ac1_a8_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10170_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10170_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a6_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL B_reg_aQ_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10172_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10172_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1466_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1466_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10173_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10173_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10174_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10174_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a85_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a85_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a89_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a89_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10175_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10175_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10176_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10176_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10177_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10177_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a70_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a70_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a86_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a90_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a90_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a94_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a94_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10185_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10185_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a7_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l1_au2_atemp2_a7_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_atemp2_a7_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_atemp2_a8_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_atemp2_a8_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_ac2_a14_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_ac2_a14_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_atemp0_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_atemp0_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ac2_a4_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ac2_a4_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a2_a_a126_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a2_a_a126_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10180_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10180_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1481_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1481_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10182_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10182_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1486_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1486_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1476_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1476_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1471_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1471_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10179_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10179_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10183_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10183_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10184_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10184_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10186_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10186_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10187_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10187_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a75_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a75_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a7_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a7_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a6_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a6_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a91_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a81_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a95_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a95_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a99_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a99_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10195_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10195_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1506_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1506_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a8_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l1_au2_ac3_a24_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_ac3_a24_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_atemp4_a45_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_atemp4_a45_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a38_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a38_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_ac3_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_ac3_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_asum_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_asum_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_atemp3_a0_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_atemp3_a0_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ap_a60_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ap_a60_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_atemp5_a4_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_atemp5_a4_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a3_a_a127_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a3_a_a127_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a3_a_a128_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a3_a_a128_I_pathsel : std_logic_vector(10 DOWNTO 0);