alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

SIGNAL add_a1401_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10142_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10142_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1391_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1391_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1396_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1396_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10139_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10139_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10143_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10143_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10144_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10144_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a70_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a70_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10145_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10145_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10146_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10146_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10147_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10147_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1411_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1411_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1426_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1426_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1421_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1421_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1416_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1416_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10149_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10149_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a4_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au1_ac3_a132_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ac3_a132_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a34_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a34_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ac3_a84_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ac3_a84_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ac3_a83_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ac3_a83_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_asum_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_asum_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10150_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10150_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10152_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10152_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10153_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10153_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10154_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10154_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a71_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a75_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a75_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10155_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10155_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10156_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10156_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10157_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10157_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a76_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a66_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a80_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a80_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a84_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a84_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10165_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10165_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10166_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10166_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1431_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1431_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1436_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1436_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10159_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10159_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1446_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1446_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1441_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1441_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a5_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a243_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a243_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a242_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a242_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a1_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a1_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_atemp3_a0_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_atemp3_a0_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a244_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ag_a244_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_ac8_a26_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_ac8_a26_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ag_a186_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ag_a186_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ag_a184_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ag_a184_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL result_t_a35_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL result_t_a35_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ag_a5_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ag_a5_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_asum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au2_asum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10160_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10160_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10162_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10162_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10163_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10163_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10164_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10164_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10167_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10167_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1451_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1451_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1456_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1456_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1461_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1461_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10169_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10169_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_atemp4_a56_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_atemp4_a56_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_ac1_a4_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_ac1_a4_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au2_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au2_ac1_a8_I_modesel : std_logic_vector(12 DOWNTO 0);