alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

-- DATE "05/03/2008 20:33:13"

-- 
-- Device: Altera EP1C6Q240C6 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	ALU IS
    PORT (
	OP : IN std_logic_vector(3 DOWNTO 0);
	reset : IN std_logic;
	Dinput : IN std_logic_vector(15 DOWNTO 0);
	clk : IN std_logic;
	write : IN std_logic;
	sel : IN std_logic;
	cin : IN std_logic;
	result : OUT std_logic_vector(15 DOWNTO 0);
	C : OUT std_logic;
	Z : OUT std_logic
	);
END ALU;

ARCHITECTURE structure OF ALU IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_OP : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_reset : std_logic;
SIGNAL ww_Dinput : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_clk : std_logic;
SIGNAL ww_write : std_logic;
SIGNAL ww_sel : std_logic;
SIGNAL ww_cin : std_logic;
SIGNAL ww_result : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_C : std_logic;
SIGNAL ww_Z : std_logic;
SIGNAL clk_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a1_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a2_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL OP_a0_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL Dinput_a0_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL reset_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL sel_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL write_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL A_reg_aprocess0_a0_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aprocess0_a0_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10118_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10118_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aprocess0_a0_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aprocess0_a0_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1366_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1366_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1361_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1361_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10123_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10123_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10292_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10292_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10124_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10124_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL cin_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL add_a1671_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1671_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1351_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1351_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a1_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL add_a1676_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1676_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1356_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1356_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10121_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10121_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL OP_a3_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL Mux_a10125_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10125_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1386_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1386_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1371_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1371_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1376_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1376_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10127_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10127_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10128_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10128_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1381_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1381_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10129_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10129_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a2_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_asum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_asum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10130_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10130_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10132_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10132_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10133_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10133_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10134_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10134_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10135_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10135_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a61_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10136_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10136_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10137_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10137_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL A_reg_aQ_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL A_reg_aQ_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1406_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL add_a1406_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Dinput_a3_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL l2_al1_au1_ac2_a56_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_ac2_a56_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_atemp3_a37_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_atemp3_a37_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l2_al1_au1_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_ac2_a7_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_ac2_a7_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL l1_au1_asum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL l1_au1_asum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Mux_a10140_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a10140_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL B_reg_aQ_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL B_reg_aQ_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL add_a1401_I_modesel : std_logic_vector(12 DOWNTO 0);