alu.map.eqn

ALU可以实现16种操作（包括加减乘除移位运算等）

A1L291 = A1L961 & (A1L861) # !A1L961 & (A1L861 & A1L981 # !A1L861 & (A1L191));


--A1L13 is add~1426
--operation mode is arithmetic

A1L13_carry_eqn = A1L42;
A1L13 = B1_Q[3] $ (A1L13_carry_eqn);

--A1L23 is add~1428
--operation mode is arithmetic

A1L23 = CARRY(!A1L42 # !B1_Q[3]);


--A1L391 is Mux~10153
--operation mode is normal

A1L391 = A1L961 & (A1L291 & (A1L13) # !A1L291 & A1L52) # !A1L961 & (A1L291);


--A1L491 is Mux~10154
--operation mode is normal

A1L491 = A1L391 & (OP[1] & !OP[3] # !OP[2]);


--M51L3 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~75
--operation mode is arithmetic

M51L3_carry_eqn = M51L2;
M51L3 = M3L5 $ M6L1 $ M51L3_carry_eqn;

--M51L4 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~77
--operation mode is arithmetic

M51L4 = CARRY(M3L5 & !M6L1 & !M51L2 # !M3L5 & (!M51L2 # !M6L1));


--A1L591 is Mux~10155
--operation mode is normal

A1L591 = OP[0] & (OP[3] & M51L3 # !OP[3] & (B2_Q[3]));


--A1L691 is Mux~10156
--operation mode is normal

A1L691 = !OP[0] & (OP[3] & (!B2_Q[3]) # !OP[3] & (B1_Q[3] # B2_Q[3]));


--A1L791 is Mux~10157
--operation mode is normal

A1L791 = A1L491 # A1L851 & (A1L591 # A1L691);


--A1L33 is add~1431
--operation mode is arithmetic

A1L33_carry_eqn = A1L82;
A1L33 = B2_Q[4] $ B1_Q[4] $ A1L33_carry_eqn;

--A1L43 is add~1433
--operation mode is arithmetic

A1L43 = CARRY(B2_Q[4] & !B1_Q[4] & !A1L82 # !B2_Q[4] & (!A1L82 # !B1_Q[4]));


--B1_Q[4] is reg:A_reg|Q[4]
--operation mode is normal

B1_Q[4]_lut_out = Dinput[4];
B1_Q[4] = DFFEAS(B1_Q[4]_lut_out, clk, reset, , B1L1, , , , );


--A1L891 is Mux~10158
--operation mode is normal

A1L891 = B2_Q[4] & (OP[0] $ (B1_Q[4] & !OP[3])) # !B2_Q[4] & OP[0] & (B1_Q[4] # OP[3]);


--A1L53 is add~1436
--operation mode is arithmetic

A1L53_carry_eqn = A1L03;
A1L53 = B2_Q[4] $ B1_Q[4] $ !A1L53_carry_eqn;

--A1L63 is add~1438
--operation mode is arithmetic

A1L63 = CARRY(B2_Q[4] & (!A1L03 # !B1_Q[4]) # !B2_Q[4] & !B1_Q[4] & !A1L03);


--A1L991 is Mux~10159
--operation mode is normal

A1L991 = OP[3] & (A1L891 & (A1L53) # !A1L891 & A1L33) # !OP[3] & (A1L891);


--A1L73 is add~1441
--operation mode is arithmetic

A1L73_carry_eqn = A1L62;
A1L73 = B1_Q[4] $ (A1L73_carry_eqn);

--A1L83 is add~1443
--operation mode is arithmetic

A1L83 = CARRY(B1_Q[4] # !A1L62);


--F5L4 is sub16:l2|adder16:l1|add4:u1|g~242
--operation mode is normal

F5L4 = B1_Q[3] & (B1_Q[2] & !B2_Q[2] # !B2_Q[3]) # !B1_Q[3] & B1_Q[2] & !B2_Q[2] & !B2_Q[3];


--F5L11 is sub16:l2|adder16:l1|add4:u1|temp3~0
--operation mode is normal

F5L11 = B1_Q[2] # !B2_Q[2];


--F5L5 is sub16:l2|adder16:l1|add4:u1|g~243
--operation mode is normal

F5L5 = B1_Q[1] & (B1_Q[0] & !B2_Q[0] # !B2_Q[1]) # !B1_Q[1] & B1_Q[0] & !B2_Q[0] & !B2_Q[1];


--F5L3 is sub16:l2|adder16:l1|add4:u1|g~1
--operation mode is normal

F5L3 = B1_Q[3] # !B2_Q[3];


--F5L6 is sub16:l2|adder16:l1|add4:u1|g~244
--operation mode is normal

F5L6 = F5L4 # F5L11 & F5L5 & F5L3;


--F6_sum[0] is sub16:l2|adder16:l1|add4:u2|sum[0]
--operation mode is normal

F6_sum[0] = B2_Q[4] $ B1_Q[4] $ (F5L6 # C2L2);


--F1L5 is adder16:l1|add4:u1|g~184
--operation mode is normal

F1L5 = B1_Q[3] & (B2_Q[3] # B2_Q[2] & B1_Q[2]) # !B1_Q[3] & B2_Q[2] & B1_Q[2] & B2_Q[3];


--A1L263 is result_t~35
--operation mode is normal

A1L263 = B2_Q[3] # B1_Q[3];


--H1_decoder_node[1][1] is lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][1]
--operation mode is normal

H1_decoder_node[1][1] = LCELL(B2_Q[1] & B1_Q[1]);


--F1L4 is adder16:l1|add4:u1|g~5
--operation mode is normal

F1L4 = F1L5 # A1L163 & A1L263 & H1_decoder_node[1][1];


--F2_sum[0] is adder16:l1|add4:u2|sum[0]
--operation mode is normal

F2_sum[0] = B2_Q[4] $ B1_Q[4] $ (F1L4 # F1L7);


--A1L002 is Mux~10160
--operation mode is normal

A1L002 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F6_sum[0] # !OP[0] & (F2_sum[0]));


--B2_Q[5] is reg:B_reg|Q[5]
--operation mode is normal

B2_Q[5]_lut_out = Dinput[5];
B2_Q[5] = DFFEAS(B2_Q[5]_lut_out, clk, reset, , B2L1, , , , );


--A1L102 is Mux~10161
--operation mode is normal

A1L102 = OP[3] & (A1L002 & (B2_Q[5]) # !A1L002 & B2_Q[3]) # !OP[3] & (A1L002);


--A1L202 is Mux~10162
--operation mode is normal

A1L202 = A1L861 & (A1L961) # !A1L861 & (A1L961 & A1L73 # !A1L961 & (A1L102));


--A1L93 is add~1446
--operation mode is arithmetic

A1L93_carry_eqn = A1L23;
A1L93 = B1_Q[4] $ (!A1L93_carry_eqn);

--A1L04 is add~1448
--operation mode is arithmetic

A1L04 = CARRY(B1_Q[4] & (!A1L23));


--A1L302 is Mux~10163
--operation mode is normal

A1L302 = A1L861 & (A1L202 & (A1L93) # !A1L202 & A1L991) # !A1L861 & (A1L202);


--A1L402 is Mux~10164
--operation mode is normal

A1L402 = A1L302 & (OP[1] & !OP[3] # !OP[2]);


--M12L1 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84
--operation mode is arithmetic

M12L1 = M51L5 $ H1_decoder_node[4][0];

--M12L2 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~86
--operation mode is arithmetic

M12L2 = CARRY(M51L5 & H1_decoder_node[4][0]);


--A1L502 is Mux~10165
--operation mode is normal

A1L502 = OP[0] & (OP[3] & M12L1 # !OP[3] & (B2_Q[4]));


--A1L602 is Mux~10166
--operation mode is normal

A1L602 = !OP[0] & (OP[3] & (!B2_Q[4]) # !OP[3] & (B1_Q[4] # B2_Q[4]));


--A1L702 is Mux~10167
--operation mode is normal

A1L702 = A1L402 # A1L851 & (A1L502 # A1L602);


--A1L14 is add~1451
--operation mode is arithmetic

A1L14_carry_eqn = A1L83;
A1L14 = B1_Q[5] $ (!A1L14_carry_eqn);

--A1L24 is add~1453
--operation mode is arithmetic

A1L24 = CARRY(!B1_Q[5] & (!A1L83));


--A1L34 is add~1456
--operation mode is arithmetic

A1L34_carry_eqn = A1L43;
A1L34 = B2_Q[5] $ B1_Q[5] $ !A1L34_carry_eqn;

--A1L44 is add~1458
--operation mode is arithmetic

A1L44 = CARRY(B2_Q[5] & (B1_Q[5] # !A1L43) # !B2_Q[5] & B1_Q[5] & !A1L43);


--B1_Q[5] is reg:A_reg|Q[5]
--operation mode is normal

B1_Q[5]_lut_out = Dinput[5];
B1_Q[5] = DFFEAS(B1_Q[5]_lut_out, clk, reset, , B1L1, , , , );


--A1L802 is Mux~10168
--operation mode is normal

A1L802 = B2_Q[5] & (OP[0] $ (B1_Q[5] & !OP[3])) # !B2_Q[5] & OP[0] & (B1_Q[5] # OP[3]);


--A1L54 is add~1461
--operation mode is arithmetic

A1L54_carry_eqn = A1L63;
A1L54 = B2_Q[5] $ B1_Q[5] $ A1L54_carry_eqn;

--A1L64 is add~1463
--operation mode is arithmetic

A1L64 = CARRY(B2_Q[5] & B1_Q[5] & !A1L63 # !B2_Q[5] & (B1_Q[5] # !A1L63));


--A1L902 is Mux~10169
--operation mode is normal

A1L902 = OP[3] & (A1L802 & (A1L54) # !A1L802 & A1L34) # !OP[3] & (A1L802);


--F6L1 is sub16:l2|adder16:l1|add4:u2|c1~4
--operation mode is normal

F6L1 = B1_Q[4] & (F5L6 # C2L2) # !B1_Q[4] & !B2_Q[4] & (F5L6 # C2L2);


--F6L81 is sub16:l2|adder16:l1|add4:u2|temp4~56
--operation mode is normal

F6L81 = B1_Q[4] & (!B2_Q[4]);


--F6_sum[1] is sub16:l2|adder16:l1|add4:u2|sum[1]
--operation mode is normal

F6_sum[1] = B2_Q[5] $ B1_Q[5] $ (F6L1 # F6L81);


--F2L1 is adder16:l1|add4:u2|c1~8
--operation mode is normal

F2L1 = B1_Q[4] & (F1L7 # F1L4 # B2_Q[4]) # !B1_Q[4] & B2_Q[4] & (F1L7 # F1L4);


--F2_sum[1] is adder16:l1|add4:u2|sum[1]
--operation mode is normal

F2_sum[1] = B2_Q[5] $ B1_Q[5] $ F2L1;


--A1L012 is Mux~10170
--operation mode is normal

A1L012 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F6_sum[1] # !OP[0] & (F2_sum[1]));


--B2_Q[6] is reg:B_reg|Q[6]
--operation mode is normal

B2_Q[6]_lut_out = Dinput[6];
B2_Q[6] = DFFEAS(B2_Q[6]_lut_out, clk, reset, , B2L1, , , , );


--A1L112 is Mux~10171
--operation mode is normal

A1L112 = OP[3] & (A1L012 & (B2_Q[6]) # !A1L012 & B2_Q[4]) # !OP[3] & (A1L012);


--A1L212 is Mux~10172
--operation mode is normal

A1L212 = A1L961 & (A1L861) # !A1L961 & (A1L861 & A1L902 # !A1L861 & (A1L112));


--A1L74 is add~1466
--operation mode is arithmetic

A1L74_carry_eqn = A1L04;
A1L74 = B1_Q[5] $ (A1L74_carry_eqn);

--A1L84 is add~1468
--operation mode is arithmetic

A1L84 = CARRY(!A1L04 # !B1_Q[5]);


--A1L312 is Mux~10173
--operation mode is normal

A1L312 = A1L961 & (A1L212 & (A1L74) # !A1L212 & A1L14) # !A1L961 & (A1L212);


--A1L412 is Mux~10174
--operation mode is normal

A1L412 = A1L312 & (OP[1] & !OP[3] # !OP[2]);


--M12L3 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~89
--operation mode is arithmetic

M12L3_carry_eqn = M12L2;
M12L3 = M51L7 $ M9L1 $ M12L3_carry_eqn;

--M12L4 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~91
--operation mode is arithmetic

M12L4 = CARRY(M51L7 & !M9L1 & !M12L2 # !M51L7 & (!M12L2 # !M9L1));


--A1L512 is Mux~10175
--operation mode is normal

A1L512 = OP[0] & (OP[3] & M12L3 # !OP[3] & (B2_Q[5]));


--A1L612 is Mux~10176
--operation mode is normal

A1L612 = !OP[0] & (OP[3] & (!B2_Q[5]) # !OP[3] & (B1_Q[5] # B2_Q[5]));


--A1L712 is Mux~10177
--operation mode is normal

A1L712 = A1L412 # A1L851 & (A1L512 # A1L612);


--A1L94 is add~1471
--operation mode is arithmetic

A1L94_carry_eqn = A1L44;
A1L94 = B2_Q[6] $ B1_Q[6] $ A1L94_carry_eqn;

--A1L05 is add~1473
--operation mode is arithmetic

A1L05 = CARRY(B2_Q[6] & !B1_Q[6] & !A1L44 # !B2_Q[6] & (!A1L44 # !B1_Q[6]));


--B1_Q[6] is reg:A_reg|Q[6]
--operation mode is normal

B1_Q[6]_lut_out = Dinput[6];
B1_Q[6] = DFFEAS(B1_Q[6]_lut_out, clk, reset, , B1L1, , , , );


--A1L812 is Mux~10178
--operation mode is normal

A1L812 = B2_Q[6] & (OP[0] $ (B1_Q[6] & !OP[3])) # !B2_Q[6] & OP[0] & (B1_Q[6] # OP[3]);


--A1L15 is add~1476
--operation mode is arithmetic

A1L15_carry_eqn = A1L64;
A1L15 = B2_Q[6] $ B1_Q[6] $ !A1L15_carry_eqn;

--A1L25 is add~1478
--operation mode is arithmetic

A1L25 = CARRY(B2_Q[6] & (!A1L64 # !B1_Q[6]) # !B2_Q[6] & !B1_Q[6] & !A1L64);


--A1L912 is Mux~10179
--operation mode is normal

A1L912 = OP[3] & (A1L812 & (A1L15) # !A1L812 & A1L94) # !OP[3] & (A1L812);


--A1L35 is add~1481
--operation mode is arithmetic

A1L35_carry_eqn = A1L24;
A1L35 = B1_Q[6] $ (A1L35_carry_eqn);

--A1L45 is add~1483
--operation mode is arithmetic

A1L45 = CARRY(B1_Q[6] # !A1L24);


--F6L2 is sub16:l2|adder16:l1|add4:u2|c2~4
--operation mode is normal

F6L2 = B2_Q[5] & (B2_Q[4] # !B1_Q[5] # !B1_Q[4]) # !B2_Q[5] & !B1_Q[5] & (B2_Q[4] # !B1_Q[4]);


--F6_temp0 is sub16:l2|adder16:l1|add4:u2|temp0
--operation mode is normal

F6_temp0 = B1_Q[5] # !B2_Q[5];


--F6L21 is sub16:l2|adder16:l1|add4:u2|sum[2]~126
--operation mode is normal

F6L21 = B2_Q[6] $ B1_Q[6];


--F6_sum[2] is sub16:l2|adder16:l1|add4:u2|sum[2]
--operation mode is normal

F6_sum[2] = F6L21 $ (F6L1 & F6_temp0 # !F6L2);


--F2L21 is adder16:l1|add4:u2|temp2~7
--operation mode is normal

F2L21 = B2_Q[4] & (B2_Q[5] # B1_Q[5]) # !B2_Q[4] & B1_Q[4] & (B2_Q[5] # B1_Q[5]);


--F2L31 is adder16:l1|add4:u2|temp2~8
--operation mode is normal

F2L31 = F2L21 & (F1L4 # F1L3 & A1L263);


--F2L2 is adder16:l1|add4:u2|c2~14
--operation mode is normal

F2L2 = B1_Q[5] & (B2_Q[5] # B2_Q[4] & B1_Q[4]) # !B1_Q[5] & B2_Q[4] & B1_Q[4] & B2_Q[5];


--A1L022 is Mux~10180
--operation mode is normal

A1L022 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F6_sum[2] # !OP[0] & (F2_sum[2]));


--B2_Q[7] is reg:B_reg|Q[7]
--operation mode is normal

B2_Q[7]_lut_out = Dinput[7];
B2_Q[7] = DFFEAS(B2_Q[7]_lut_out, clk, reset, , B2L1, , , , );


--A1L122 is Mux~10181
--operation mode is normal

A1L122 = OP[3] & (A1L022 & (B2_Q[7]) # !A1L022 & B2_Q[5]) # !OP[3] & (A1L022);


--A1L222 is Mux~10182
--operation mode is normal

A1L222 = A1L861 & (A1L961) # !A1L861 & (A1L961 & A1L35 # !A1L961 & (A1L122));


--A1L55 is add~1486
--operation mode is arithmetic

A1L55_carry_eqn = A1L84;
A1L55 = B1_Q[6] $ (!A1L55_carry_eqn);

--A1L65 is add~1488
--operation mode is arithmetic

A1L65 = CARRY(B1_Q[6] & (!A1L84));


--A1L322 is Mux~10183
--operation mode is normal

A1L322 = A1L861 & (A1L222 & (A1L55) # !A1L222 & A1L912) # !A1L861 & (A1L222);


--A1L422 is Mux~10184
--operation mode is normal

A1L422 = A1L322 & (OP[1] & !OP[3] # !OP[2]);


--M12L5 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~94
--operation mode is arithmetic

M12L5_carry_eqn = M12L4;
M12L5 = M51L9 $ M81L1 $ !M12L5_carry_eqn;

--M12L6 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~96