alu.map.eqn

ALU可以实现16种操作（包括加减乘除移位运算等）

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--A1L851 is Mux~10118
--operation mode is normal

A1L851 = OP[2] & (!OP[1]);


--B2_Q[0] is reg:B_reg|Q[0]
--operation mode is normal

B2_Q[0]_lut_out = Dinput[0];
B2_Q[0] = DFFEAS(B2_Q[0]_lut_out, clk, reset, , B2L1, , , , );


--A1L951 is Mux~10119
--operation mode is normal

A1L951 = A1L851 & (OP[0] & H1_decoder_node[0][0] # !OP[0] & (!B2_Q[0]));


--A1L1 is add~1351
--operation mode is arithmetic

A1L1_carry_eqn = A1L031;
A1L1 = B2_Q[0] $ B1_Q[0] $ A1L1_carry_eqn;

--A1L2 is add~1353
--operation mode is arithmetic

A1L2 = CARRY(B2_Q[0] & !B1_Q[0] & !A1L031 # !B2_Q[0] & (!A1L031 # !B1_Q[0]));


--A1L3 is add~1356
--operation mode is arithmetic

A1L3_carry_eqn = A1L231;
A1L3 = B2_Q[0] $ B1_Q[0] $ !A1L3_carry_eqn;

--A1L4 is add~1358
--operation mode is arithmetic

A1L4 = CARRY(B2_Q[0] & (!A1L231 # !B1_Q[0]) # !B2_Q[0] & !B1_Q[0] & !A1L231);


--B2_Q[1] is reg:B_reg|Q[1]
--operation mode is normal

B2_Q[1]_lut_out = Dinput[1];
B2_Q[1] = DFFEAS(B2_Q[1]_lut_out, clk, reset, , B2L1, , , , );


--A1L061 is Mux~10120
--operation mode is normal

A1L061 = OP[1] & (A1L3 # !OP[0]) # !OP[1] & (B2_Q[1] & OP[0]);


--A1L161 is Mux~10121
--operation mode is normal

A1L161 = !OP[2] & A1L061 & (A1L1 # OP[0]);


--B1_Q[0] is reg:A_reg|Q[0]
--operation mode is normal

B1_Q[0]_lut_out = Dinput[0];
B1_Q[0] = DFFEAS(B1_Q[0]_lut_out, clk, reset, , B1L1, , , , );


--A1L261 is Mux~10122
--operation mode is normal

A1L261 = B2_Q[0] & (B1_Q[0] $ OP[0] # !OP[1]) # !B2_Q[0] & B1_Q[0] & (OP[0] $ !OP[1]);


--F1L21 is adder16:l1|add4:u1|sum~0
--operation mode is normal

F1L21 = B2_Q[0] $ B1_Q[0];


--A1L5 is add~1361
--operation mode is arithmetic

A1L5 = !B1_Q[0];

--A1L6 is add~1363
--operation mode is arithmetic

A1L6 = CARRY(B1_Q[0]);


--A1L7 is add~1366
--operation mode is arithmetic

A1L7 = !B1_Q[0];

--A1L8 is add~1368
--operation mode is arithmetic

A1L8 = CARRY(B1_Q[0]);


--A1L361 is Mux~10123
--operation mode is normal

A1L361 = OP[0] & A1L5 # !OP[0] & (A1L7);


--A1L461 is Mux~10124
--operation mode is normal

A1L461 = OP[2] & (OP[1] & (A1L233) # !OP[1] & A1L261) # !OP[2] & (OP[1] & A1L261 # !OP[1] & (A1L233));


--A1L561 is Mux~10125
--operation mode is normal

A1L561 = OP[3] & (A1L951 # A1L161) # !OP[3] & (A1L461);


--A1L9 is add~1371
--operation mode is arithmetic

A1L9_carry_eqn = A1L2;
A1L9 = B2_Q[1] $ B1_Q[1] $ !A1L9_carry_eqn;

--A1L01 is add~1373
--operation mode is arithmetic

A1L01 = CARRY(B2_Q[1] & (B1_Q[1] # !A1L2) # !B2_Q[1] & B1_Q[1] & !A1L2);


--B1_Q[1] is reg:A_reg|Q[1]
--operation mode is normal

B1_Q[1]_lut_out = Dinput[1];
B1_Q[1] = DFFEAS(B1_Q[1]_lut_out, clk, reset, , B1L1, , , , );


--A1L661 is Mux~10126
--operation mode is normal

A1L661 = B1_Q[1] & (OP[0] $ (B2_Q[1] & !OP[3])) # !B1_Q[1] & OP[0] & (B2_Q[1] # OP[3]);


--A1L11 is add~1376
--operation mode is arithmetic

A1L11_carry_eqn = A1L4;
A1L11 = B2_Q[1] $ B1_Q[1] $ A1L11_carry_eqn;

--A1L21 is add~1378
--operation mode is arithmetic

A1L21 = CARRY(B2_Q[1] & B1_Q[1] & !A1L4 # !B2_Q[1] & (B1_Q[1] # !A1L4));


--A1L761 is Mux~10127
--operation mode is normal

A1L761 = OP[3] & (A1L661 & (A1L11) # !A1L661 & A1L9) # !OP[3] & (A1L661);


--A1L861 is Mux~10128
--operation mode is normal

A1L861 = OP[1] & (OP[0] # !OP[2]);


--A1L31 is add~1381
--operation mode is arithmetic

A1L31_carry_eqn = A1L8;
A1L31 = B1_Q[1] $ (!A1L31_carry_eqn);

--A1L41 is add~1383
--operation mode is arithmetic

A1L41 = CARRY(!B1_Q[1] & (!A1L8));


--A1L961 is Mux~10129
--operation mode is normal

A1L961 = OP[2] & OP[1];


--F5_sum[1] is sub16:l2|adder16:l1|add4:u1|sum[1]
--operation mode is normal

F5_sum[1] = B2_Q[1] $ B1_Q[1] $ (B1_Q[0] # !B2_Q[0]);


--F1_sum[1] is adder16:l1|add4:u1|sum[1]
--operation mode is normal

F1_sum[1] = B2_Q[1] $ B1_Q[1] $ (B2_Q[0] & B1_Q[0]);


--A1L071 is Mux~10130
--operation mode is normal

A1L071 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F5_sum[1] # !OP[0] & (F1_sum[1]));


--B2_Q[2] is reg:B_reg|Q[2]
--operation mode is normal

B2_Q[2]_lut_out = Dinput[2];
B2_Q[2] = DFFEAS(B2_Q[2]_lut_out, clk, reset, , B2L1, , , , );


--A1L171 is Mux~10131
--operation mode is normal

A1L171 = OP[3] & (A1L071 & (B2_Q[2]) # !A1L071 & B2_Q[0]) # !OP[3] & (A1L071);


--A1L271 is Mux~10132
--operation mode is normal

A1L271 = A1L861 & (A1L961) # !A1L861 & (A1L961 & A1L31 # !A1L961 & (A1L171));


--A1L51 is add~1386
--operation mode is arithmetic

A1L51_carry_eqn = A1L6;
A1L51 = B1_Q[1] $ (A1L51_carry_eqn);

--A1L61 is add~1388
--operation mode is arithmetic

A1L61 = CARRY(!A1L6 # !B1_Q[1]);


--A1L371 is Mux~10133
--operation mode is normal

A1L371 = A1L861 & (A1L271 & (A1L51) # !A1L271 & A1L761) # !A1L861 & (A1L271);


--A1L471 is Mux~10134
--operation mode is normal

A1L471 = A1L371 & (OP[1] & !OP[3] # !OP[2]);


--A1L571 is Mux~10135
--operation mode is normal

A1L571 = !OP[3] & (B2_Q[1] # B1_Q[1] & !OP[0]);


--M3L1 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61
--operation mode is arithmetic

M3L1 = H1_decoder_node[0][1] $ H1_decoder_node[1][0];

--M3L2 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~63
--operation mode is arithmetic

M3L2 = CARRY(H1_decoder_node[0][1] & H1_decoder_node[1][0]);


--A1L671 is Mux~10136
--operation mode is normal

A1L671 = OP[3] & (OP[0] & M3L1 # !OP[0] & (!B2_Q[1]));


--A1L771 is Mux~10137
--operation mode is normal

A1L771 = A1L471 # A1L851 & (A1L571 # A1L671);


--A1L71 is add~1391
--operation mode is arithmetic

A1L71_carry_eqn = A1L01;
A1L71 = B2_Q[2] $ B1_Q[2] $ A1L71_carry_eqn;

--A1L81 is add~1393
--operation mode is arithmetic

A1L81 = CARRY(B2_Q[2] & !B1_Q[2] & !A1L01 # !B2_Q[2] & (!A1L01 # !B1_Q[2]));


--B1_Q[2] is reg:A_reg|Q[2]
--operation mode is normal

B1_Q[2]_lut_out = Dinput[2];
B1_Q[2] = DFFEAS(B1_Q[2]_lut_out, clk, reset, , B1L1, , , , );


--A1L871 is Mux~10138
--operation mode is normal

A1L871 = B2_Q[2] & (OP[0] $ (B1_Q[2] & !OP[3])) # !B2_Q[2] & OP[0] & (B1_Q[2] # OP[3]);


--A1L91 is add~1396
--operation mode is arithmetic

A1L91_carry_eqn = A1L21;
A1L91 = B2_Q[2] $ B1_Q[2] $ !A1L91_carry_eqn;

--A1L02 is add~1398
--operation mode is arithmetic

A1L02 = CARRY(B2_Q[2] & (!A1L21 # !B1_Q[2]) # !B2_Q[2] & !B1_Q[2] & !A1L21);


--A1L971 is Mux~10139
--operation mode is normal

A1L971 = OP[3] & (A1L871 & (A1L91) # !A1L871 & A1L71) # !OP[3] & (A1L871);


--A1L12 is add~1401
--operation mode is arithmetic

A1L12_carry_eqn = A1L41;
A1L12 = B1_Q[2] $ (A1L12_carry_eqn);

--A1L22 is add~1403
--operation mode is arithmetic

A1L22 = CARRY(B1_Q[2] # !A1L41);


--F5L21 is sub16:l2|adder16:l1|add4:u1|temp3~37
--operation mode is normal

F5L21 = B1_Q[1] & (!B2_Q[1]);


--F5L1 is sub16:l2|adder16:l1|add4:u1|c2~56
--operation mode is normal

F5L1 = B1_Q[1] & (B1_Q[0] # !B2_Q[0]) # !B1_Q[1] & !B2_Q[1] & (B1_Q[0] # !B2_Q[0]);


--F5_sum[2] is sub16:l2|adder16:l1|add4:u1|sum[2]
--operation mode is normal

F5_sum[2] = B2_Q[2] $ B1_Q[2] $ (F5L21 # F5L1);


--F1L1 is adder16:l1|add4:u1|c2~7
--operation mode is normal

F1L1 = B2_Q[1] & (B1_Q[1] # B1_Q[0] & B2_Q[0]) # !B2_Q[1] & B1_Q[0] & B2_Q[0] & B1_Q[1];


--F1_sum[2] is adder16:l1|add4:u1|sum[2]
--operation mode is normal

F1_sum[2] = B2_Q[2] $ B1_Q[2] $ F1L1;


--A1L081 is Mux~10140
--operation mode is normal

A1L081 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F5_sum[2] # !OP[0] & (F1_sum[2]));


--B2_Q[3] is reg:B_reg|Q[3]
--operation mode is normal

B2_Q[3]_lut_out = Dinput[3];
B2_Q[3] = DFFEAS(B2_Q[3]_lut_out, clk, reset, , B2L1, , , , );


--A1L181 is Mux~10141
--operation mode is normal

A1L181 = OP[3] & (A1L081 & (B2_Q[3]) # !A1L081 & B2_Q[1]) # !OP[3] & (A1L081);


--A1L281 is Mux~10142
--operation mode is normal

A1L281 = A1L861 & (A1L961) # !A1L861 & (A1L961 & A1L12 # !A1L961 & (A1L181));


--A1L32 is add~1406
--operation mode is arithmetic

A1L32_carry_eqn = A1L61;
A1L32 = B1_Q[2] $ (!A1L32_carry_eqn);

--A1L42 is add~1408
--operation mode is arithmetic

A1L42 = CARRY(B1_Q[2] & (!A1L61));


--A1L381 is Mux~10143
--operation mode is normal

A1L381 = A1L861 & (A1L281 & (A1L32) # !A1L281 & A1L971) # !A1L861 & (A1L281);


--A1L481 is Mux~10144
--operation mode is normal

A1L481 = A1L381 & (OP[1] & !OP[3] # !OP[2]);


--M51L1 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~70
--operation mode is arithmetic

M51L1 = M3L3 $ H1_decoder_node[2][0];

--M51L2 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~72
--operation mode is arithmetic

M51L2 = CARRY(M3L3 & H1_decoder_node[2][0]);


--A1L581 is Mux~10145
--operation mode is normal

A1L581 = OP[0] & (OP[3] & M51L1 # !OP[3] & (B2_Q[2]));


--A1L681 is Mux~10146
--operation mode is normal

A1L681 = !OP[0] & (OP[3] & (!B2_Q[2]) # !OP[3] & (B1_Q[2] # B2_Q[2]));


--A1L781 is Mux~10147
--operation mode is normal

A1L781 = A1L481 # A1L851 & (A1L581 # A1L681);


--A1L52 is add~1411
--operation mode is arithmetic

A1L52_carry_eqn = A1L22;
A1L52 = B1_Q[3] $ (!A1L52_carry_eqn);

--A1L62 is add~1413
--operation mode is arithmetic

A1L62 = CARRY(!B1_Q[3] & (!A1L22));


--A1L72 is add~1416
--operation mode is arithmetic

A1L72_carry_eqn = A1L81;
A1L72 = B2_Q[3] $ B1_Q[3] $ !A1L72_carry_eqn;

--A1L82 is add~1418
--operation mode is arithmetic

A1L82 = CARRY(B2_Q[3] & (B1_Q[3] # !A1L81) # !B2_Q[3] & B1_Q[3] & !A1L81);


--B1_Q[3] is reg:A_reg|Q[3]
--operation mode is normal

B1_Q[3]_lut_out = Dinput[3];
B1_Q[3] = DFFEAS(B1_Q[3]_lut_out, clk, reset, , B1L1, , , , );


--A1L881 is Mux~10148
--operation mode is normal

A1L881 = B2_Q[3] & (OP[0] $ (B1_Q[3] & !OP[3])) # !B2_Q[3] & OP[0] & (B1_Q[3] # OP[3]);


--A1L92 is add~1421
--operation mode is arithmetic

A1L92_carry_eqn = A1L02;
A1L92 = B2_Q[3] $ B1_Q[3] $ A1L92_carry_eqn;

--A1L03 is add~1423
--operation mode is arithmetic

A1L03 = CARRY(B2_Q[3] & B1_Q[3] & !A1L02 # !B2_Q[3] & (B1_Q[3] # !A1L02));


--A1L981 is Mux~10149
--operation mode is normal

A1L981 = OP[3] & (A1L881 & (A1L92) # !A1L881 & A1L72) # !OP[3] & (A1L881);


--F5L2 is sub16:l2|adder16:l1|add4:u1|c3~132
--operation mode is normal

F5L2 = B1_Q[2] & (F5L21 # F5L1 # !B2_Q[2]) # !B1_Q[2] & !B2_Q[2] & (F5L21 # F5L1);


--F5_sum[3] is sub16:l2|adder16:l1|add4:u1|sum[3]
--operation mode is normal

F5_sum[3] = B2_Q[3] $ B1_Q[3] $ F5L2;


--F1L2 is adder16:l1|add4:u1|c3~83
--operation mode is normal

F1L2 = B1_Q[2] & (B2_Q[2] # B1_Q[1] & B2_Q[1]) # !B1_Q[2] & B1_Q[1] & B2_Q[1] & B2_Q[2];


--H1_decoder_node[0][0] is lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][0]
--operation mode is normal

H1_decoder_node[0][0] = LCELL(B2_Q[0] & B1_Q[0]);


--A1L163 is result_t~34
--operation mode is normal

A1L163 = B2_Q[2] # B1_Q[2];


--F1L3 is adder16:l1|add4:u1|c3~84
--operation mode is normal

F1L3 = H1_decoder_node[0][0] & A1L163 & (B2_Q[1] # B1_Q[1]);


--F1_sum[3] is adder16:l1|add4:u1|sum[3]
--operation mode is normal

F1_sum[3] = B2_Q[3] $ B1_Q[3] $ (F1L2 # F1L3);


--A1L091 is Mux~10150
--operation mode is normal

A1L091 = OP[3] & (OP[0]) # !OP[3] & (OP[0] & !F5_sum[3] # !OP[0] & (F1_sum[3]));


--B2_Q[4] is reg:B_reg|Q[4]
--operation mode is normal

B2_Q[4]_lut_out = Dinput[4];
B2_Q[4] = DFFEAS(B2_Q[4]_lut_out, clk, reset, , B2L1, , , , );


--A1L191 is Mux~10151
--operation mode is normal

A1L191 = OP[3] & (A1L091 & (B2_Q[4]) # !A1L091 & B2_Q[2]) # !OP[3] & (A1L091);


--A1L291 is Mux~10152
--operation mode is normal