alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

	cout0 => add_a1363,
	cout1 => add_a1363COUT1_1702);

Mux_a10123_I : cyclone_lcell
-- Equation(s):
-- Mux_a10123 = OP_a0_a_acombout & (add_a1361) # !OP_a0_a_acombout & add_a1366

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F0CC",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => add_a1366,
	datac => add_a1361,
	datad => OP_a0_a_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10123);

Mux_a10292_I : cyclone_lcell
-- Equation(s):
-- Mux_a10292 = OP_a1_a_acombout & (Mux_a10123) # !OP_a1_a_acombout & (A_reg_aQ_a0_a $ B_reg_aQ_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F606",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => A_reg_aQ_a0_a,
	datab => B_reg_aQ_a0_a,
	datac => OP_a1_a_acombout,
	datad => Mux_a10123,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10292);

Mux_a10124_I : cyclone_lcell
-- Equation(s):
-- Mux_a10124 = OP_a1_a_acombout & (OP_a2_a_acombout & (Mux_a10292) # !OP_a2_a_acombout & Mux_a10122) # !OP_a1_a_acombout & (OP_a2_a_acombout & Mux_a10122 # !OP_a2_a_acombout & (Mux_a10292))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F960",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => OP_a1_a_acombout,
	datab => OP_a2_a_acombout,
	datac => Mux_a10122,
	datad => Mux_a10292,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10124);

cin_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_cin,
	combout => cin_acombout);

add_a1673_I : cyclone_lcell
-- Equation(s):
-- add_a1673 = CARRY(cin_acombout)
-- add_a1673COUT1_1728 = CARRY(cin_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFAA",
	output_mode => "none")
-- pragma translate_on
PORT MAP (
	dataa => cin_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	cout0 => add_a1673,
	cout1 => add_a1673COUT1_1728);

add_a1351_I : cyclone_lcell
-- Equation(s):
-- add_a1351 = A_reg_aQ_a0_a $ B_reg_aQ_a0_a $ add_a1673
-- add_a1353 = CARRY(A_reg_aQ_a0_a & !B_reg_aQ_a0_a & !add_a1673 # !A_reg_aQ_a0_a & (!add_a1673 # !B_reg_aQ_a0_a))
-- add_a1353COUT1_1729 = CARRY(A_reg_aQ_a0_a & !B_reg_aQ_a0_a & !add_a1673COUT1_1728 # !A_reg_aQ_a0_a & (!add_a1673COUT1_1728 # !B_reg_aQ_a0_a))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9617",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => A_reg_aQ_a0_a,
	datab => B_reg_aQ_a0_a,
	cin0 => add_a1673,
	cin1 => add_a1673COUT1_1728,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1351,
	cout0 => add_a1353,
	cout1 => add_a1353COUT1_1729);

Dinput_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Dinput(1),
	combout => Dinput_a1_a_acombout);

add_a1678_I : cyclone_lcell
-- Equation(s):
-- add_a1678 = CARRY(!cin_acombout)
-- add_a1678COUT1_1742 = CARRY(!cin_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF55",
	output_mode => "none")
-- pragma translate_on
PORT MAP (
	dataa => cin_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	cout0 => add_a1678,
	cout1 => add_a1678COUT1_1742);

add_a1356_I : cyclone_lcell
-- Equation(s):
-- add_a1356 = A_reg_aQ_a0_a $ B_reg_aQ_a0_a $ !add_a1678
-- add_a1358 = CARRY(A_reg_aQ_a0_a & B_reg_aQ_a0_a & !add_a1678 # !A_reg_aQ_a0_a & (B_reg_aQ_a0_a # !add_a1678))
-- add_a1358COUT1_1743 = CARRY(A_reg_aQ_a0_a & B_reg_aQ_a0_a & !add_a1678COUT1_1742 # !A_reg_aQ_a0_a & (B_reg_aQ_a0_a # !add_a1678COUT1_1742))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "694D",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => A_reg_aQ_a0_a,
	datab => B_reg_aQ_a0_a,
	cin0 => add_a1678,
	cin1 => add_a1678COUT1_1742,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1356,
	cout0 => add_a1358,
	cout1 => add_a1358COUT1_1743);

B_reg_aQ_a1_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a10120 = OP_a1_a_acombout & (add_a1356 # !OP_a0_a_acombout) # !OP_a1_a_acombout & OP_a0_a_acombout & B2_Q[1]
-- B_reg_aQ_a1_a = DFFEAS(Mux_a10120, GLOBAL(clk_acombout), GLOBAL(reset_acombout), , B_reg_aprocess0_a0, Dinput_a1_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "EA62",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a1_a_acombout,
	datab => OP_a0_a_acombout,
	datac => Dinput_a1_a_acombout,
	datad => add_a1356,
	aclr => ALT_INV_reset_acombout,
	sload => VCC,
	ena => B_reg_aprocess0_a0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10120,
	regout => B_reg_aQ_a1_a);

Mux_a10121_I : cyclone_lcell
-- Equation(s):
-- Mux_a10121 = !OP_a2_a_acombout & Mux_a10120 & (OP_a0_a_acombout # add_a1351)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "5400",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => OP_a2_a_acombout,
	datab => OP_a0_a_acombout,
	datac => add_a1351,
	datad => Mux_a10120,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10121);

OP_a3_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(3),
	combout => OP_a3_a_acombout);

Mux_a10125_I : cyclone_lcell
-- Equation(s):
-- Mux_a10125 = OP_a3_a_acombout & (Mux_a10121 # Mux_a10119) # !OP_a3_a_acombout & Mux_a10124

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FCAA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => Mux_a10124,
	datab => Mux_a10121,
	datac => Mux_a10119,
	datad => OP_a3_a_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10125);

A_reg_aQ_a1_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a10126 = OP_a3_a_acombout & (OP_a0_a_acombout) # !OP_a3_a_acombout & (B_reg_aQ_a1_a & (B1_Q[1] $ OP_a0_a_acombout) # !B