alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(2),
	combout => OP_a2_a_acombout);

OP_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(0),
	combout => OP_a0_a_acombout);

Dinput_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Dinput(0),
	combout => Dinput_a0_a_acombout);

reset_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_reset,
	combout => reset_acombout);

sel_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_sel,
	combout => sel_acombout);

write_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_write,
	combout => write_acombout);

A_reg_aprocess0_a0_I : cyclone_lcell
-- Equation(s):
-- A_reg_aprocess0_a0 = !sel_acombout & (write_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3300",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => sel_acombout,
	datad => write_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => A_reg_aprocess0_a0);

A_reg_aQ_a0_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a10122 = B_reg_aQ_a0_a & (OP_a0_a_acombout $ B1_Q[0] # !OP_a1_a_acombout) # !B_reg_aQ_a0_a & B1_Q[0] & (OP_a1_a_acombout $ !OP_a0_a_acombout)
-- A_reg_aQ_a0_a = DFFEAS(Mux_a10122, GLOBAL(clk_acombout), GLOBAL(reset_acombout), , A_reg_aprocess0_a0, Dinput_a0_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "7D90",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => OP_a1_a_acombout,
	datab => OP_a0_a_acombout,
	datac => Dinput_a0_a_acombout,
	datad => B_reg_aQ_a0_a,
	aclr => ALT_INV_reset_acombout,
	sload => VCC,
	ena => A_reg_aprocess0_a0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10122,
	regout => A_reg_aQ_a0_a);

result_t_a0 : cyclone_lcell
-- Equation(s):
-- mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a = LCELL(B_reg_aQ_a0_a & A_reg_aQ_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F000",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => B_reg_aQ_a0_a,
	datad => A_reg_aQ_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a);

Mux_a10118_I : cyclone_lcell
-- Equation(s):
-- Mux_a10118 = OP_a2_a_acombout & !OP_a1_a_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00F0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => OP_a2_a_acombout,
	datad => OP_a1_a_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10118);

B_reg_aprocess0_a0_I : cyclone_lcell
-- Equation(s):
-- B_reg_aprocess0_a0 = sel_acombout & (write_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CC00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => sel_acombout,
	datad => write_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => B_reg_aprocess0_a0);

B_reg_aQ_a0_a_aI : cyclone_lcell
-- Equation(s):
-- Mux_a10119 = Mux_a10118 & (OP_a0_a_acombout & mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a # !OP_a0_a_acombout & (!B2_Q[0]))
-- B_reg_aQ_a0_a = DFFEAS(Mux_a10119, GLOBAL(clk_acombout), GLOBAL(reset_acombout), , B_reg_aprocess0_a0, Dinput_a0_a_acombout, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "qfbk",
	lut_mask => "8B00",
	output_mode => "reg_and_comb")
-- pragma translate_on
PORT MAP (
	clk => clk_acombout,
	dataa => mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a,
	datab => OP_a0_a_acombout,
	datac => Dinput_a0_a_acombout,
	datad => Mux_a10118,
	aclr => ALT_INV_reset_acombout,
	sload => VCC,
	ena => B_reg_aprocess0_a0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => Mux_a10119,
	regout => B_reg_aQ_a0_a);

add_a1366_I : cyclone_lcell
-- Equation(s):
-- add_a1366 = !A_reg_aQ_a0_a
-- add_a1368 = CARRY(A_reg_aQ_a0_a)
-- add_a1368COUT1_1715 = CARRY(A_reg_aQ_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "55AA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => A_reg_aQ_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1366,
	cout0 => add_a1368,
	cout1 => add_a1368COUT1_1715);

add_a1361_I : cyclone_lcell
-- Equation(s):
-- add_a1361 = !A_reg_aQ_a0_a
-- add_a1363 = CARRY(A_reg_aQ_a0_a)
-- add_a1363COUT1_1702 = CARRY(A_reg_aQ_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "33CC",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => A_reg_aQ_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a1361,