alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

SIGNAL l1_au3_asum_a3_a : std_logic;
SIGNAL Mux_a10230 : std_logic;
SIGNAL Dinput_a12_a_acombout : std_logic;
SIGNAL l2_al1_au3_asum_a3_a_a118 : std_logic;
SIGNAL l2_al1_au3_asum_a3_a_a117 : std_logic;
SIGNAL Mux_a10231 : std_logic;
SIGNAL Mux_a10232 : std_logic;
SIGNAL add_a1568 : std_logic;
SIGNAL add_a1568COUT1_1710 : std_logic;
SIGNAL add_a1586 : std_logic;
SIGNAL Mux_a10233 : std_logic;
SIGNAL Mux_a10234 : std_logic;
SIGNAL Mux_a10237 : std_logic;
SIGNAL B_reg_aQ_a12_a : std_logic;
SIGNAL A_reg_aQ_a12_a : std_logic;
SIGNAL add_a1573 : std_logic;
SIGNAL add_a1573COUT1_1724 : std_logic;
SIGNAL add_a1601 : std_logic;
SIGNAL l2_al1_au3_ap_a72 : std_logic;
SIGNAL l2_al1_au3_ap : std_logic;
SIGNAL l2_al1_au3_ag_a221 : std_logic;
SIGNAL l2_al1_au3_ag_a222 : std_logic;
SIGNAL l2_al1_ac12_a106 : std_logic;
SIGNAL l2_al1_acout_a189 : std_logic;
SIGNAL l2_al1_au4_asum_a0_a : std_logic;
SIGNAL Dinput_a13_a_acombout : std_logic;
SIGNAL l1_au3_ag_a102 : std_logic;
SIGNAL l1_au3_ag_a101 : std_logic;
SIGNAL l1_au3_ag_a100 : std_logic;
SIGNAL l1_ac12_a52 : std_logic;
SIGNAL result_t_a43 : std_logic;
SIGNAL l1_ac12_a1 : std_logic;
SIGNAL l1_ac12_a53 : std_logic;
SIGNAL l1_au4_asum_a0_a : std_logic;
SIGNAL Mux_a10240 : std_logic;
SIGNAL Mux_a10241 : std_logic;
SIGNAL Mux_a10242 : std_logic;
SIGNAL add_a1588 : std_logic;
SIGNAL add_a1588COUT1_1711 : std_logic;
SIGNAL add_a1606 : std_logic;
SIGNAL Mux_a10238 : std_logic;
SIGNAL add_a1583 : std_logic;
SIGNAL add_a1583COUT1_1752 : std_logic;
SIGNAL add_a1596 : std_logic;
SIGNAL add_a1578 : std_logic;
SIGNAL add_a1578COUT1_1738 : std_logic;
SIGNAL add_a1591 : std_logic;
SIGNAL Mux_a10239 : std_logic;
SIGNAL Mux_a10243 : std_logic;
SIGNAL Mux_a10244 : std_logic;
SIGNAL Mux_a10246 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a5_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a6_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a83 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a86 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a7_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a93 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a93COUT1_111 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a96 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a97 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a97COUT1_125 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a100 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a121 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a121COUT1_150 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a124 : std_logic;
SIGNAL Mux_a10245 : std_logic;
SIGNAL Mux_a10247 : std_logic;
SIGNAL B_reg_aQ_a13_a : std_logic;
SIGNAL A_reg_aQ_a13_a : std_logic;
SIGNAL add_a1608 : std_logic;
SIGNAL add_a1626 : std_logic;
SIGNAL add_a1603 : std_logic;
SIGNAL add_a1611 : std_logic;
SIGNAL add_a1598 : std_logic;
SIGNAL add_a1621 : std_logic;
SIGNAL add_a1593 : std_logic;
SIGNAL add_a1616 : std_logic;
SIGNAL Mux_a10248 : std_logic;
SIGNAL Mux_a10249 : std_logic;
SIGNAL l2_al1_au4_ac1_a4 : std_logic;
SIGNAL l2_al1_au4_atemp4_a59 : std_logic;
SIGNAL l2_al1_au4_asum_a1_a : std_logic;
SIGNAL Dinput_a14_a_acombout : std_logic;
SIGNAL l1_au4_ac1_a8 : std_logic;
SIGNAL l1_au4_asum_a1_a : std_logic;
SIGNAL Mux_a10250 : std_logic;
SIGNAL Mux_a10251 : std_logic;
SIGNAL Mux_a10252 : std_logic;
SIGNAL Mux_a10253 : std_logic;
SIGNAL Mux_a10254 : std_logic;
SIGNAL Mux_a10256 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a98 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a98COUT1_112 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a101 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a7_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a6_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a88 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a88COUT1_110 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a91 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a102 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a102COUT1_126 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a105 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a126 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a126COUT1_151 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a129 : std_logic;
SIGNAL Mux_a10255 : std_logic;
SIGNAL Mux_a10257 : std_logic;
SIGNAL B_reg_aQ_a14_a : std_logic;
SIGNAL A_reg_aQ_a14_a : std_logic;
SIGNAL add_a1623 : std_logic;
SIGNAL add_a1623COUT1_1753 : std_logic;
SIGNAL add_a1631 : std_logic;
SIGNAL add_a1618 : std_logic;
SIGNAL add_a1618COUT1_1739 : std_logic;
SIGNAL add_a1636 : std_logic;
SIGNAL Mux_a10259 : std_logic;
SIGNAL Mux_a10260 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a7_a_a7_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a93 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a93COUT1_111 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a96 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a107 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a107COUT1_127 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a110 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a131 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a131COUT1_152 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a134 : std_logic;
SIGNAL Mux_a10258 : std_logic;
SIGNAL Mux_a10261 : std_logic;
SIGNAL add_a1628 : std_logic;
SIGNAL add_a1628COUT1_1712 : std_logic;
SIGNAL add_a1641 : std_logic;
SIGNAL add_a1613 : std_logic;
SIGNAL add_a1613COUT1_1725 : std_logic;
SIGNAL add_a1646 : std_logic;
SIGNAL Mux_a10263 : std_logic;
SIGNAL l2_al1_au4_atemp1_a17 : std_logic;
SIGNAL l2_al1_au4_ac2 : std_logic;
SIGNAL result_t_a70 : std_logic;
SIGNAL l1_au4_atemp2_a3 : std_logic;
SIGNAL l1_au4_ac2_a14 : std_logic;
SIGNAL l1_au4_ac2 : std_logic;
SIGNAL Mux_a10262 : std_logic;
SIGNAL Mux_a10264 : std_logic;
SIGNAL Mux_a10265 : std_logic;
SIGNAL Mux_a10266 : std_logic;
SIGNAL l1_au4_atemp4_a82 : std_logic;
SIGNAL result_t_a44 : std_logic;
SIGNAL l1_au4_atemp5 : std_logic;
SIGNAL l1_au4_ac3_a24 : std_logic;
SIGNAL l1_au4_atemp4_a83 : std_logic;
SIGNAL Dinput_a15_a_acombout : std_logic;
SIGNAL A_reg_aQ_a15_a : std_logic;
SIGNAL B_reg_aQ_a15_a : std_logic;
SIGNAL l2_al1_au4_asum_a3_a_a107 : std_logic;
SIGNAL l1_au4_asum_a3_a : std_logic;
SIGNAL Mux_a10269 : std_logic;
SIGNAL l2_al1_au4_atemp3_a40 : std_logic;
SIGNAL l2_al1_au4_ac3_a24 : std_logic;
SIGNAL l2_al1_au4_atemp3_a0 : std_logic;
SIGNAL l2_al1_au4_atemp0 : std_logic;
SIGNAL l2_al1_au4_atemp5_a0 : std_logic;
SIGNAL l2_al1_au4_atemp2_a3 : std_logic;
SIGNAL l2_al1_au4_asum_a3_a : std_logic;
SIGNAL Mux_a10270 : std_logic;
SIGNAL add_a1648 : std_logic;
SIGNAL add_a1648COUT1_1726 : std_logic;
SIGNAL add_a1661 : std_logic;
SIGNAL Mux_a10271 : std_logic;
SIGNAL add_a1638 : std_logic;
SIGNAL add_a1638COUT1_1740 : std_logic;
SIGNAL add_a1651 : std_logic;
SIGNAL add_a1633 : std_logic;
SIGNAL add_a1633COUT1_1754 : std_logic;
SIGNAL add_a1656 : std_logic;
SIGNAL Mux_a10267 : std_logic;
SIGNAL Mux_a10268 : std_logic;
SIGNAL add_a1643 : std_logic;
SIGNAL add_a1643COUT1_1713 : std_logic;
SIGNAL add_a1666 : std_logic;
SIGNAL Mux_a10272 : std_logic;
SIGNAL Mux_a10273 : std_logic;
SIGNAL Mux_a10274 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a98 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a98COUT1_112 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a3_a_aadder_aresult_node_acs_buffer_a0_a_a101 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a112 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a112COUT1_128 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a115 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a136 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a139 : std_logic;
SIGNAL Mux_a10275 : std_logic;
SIGNAL Mux_a10276 : std_logic;
SIGNAL Mux_a10291 : std_logic;
SIGNAL add_a1653 : std_logic;
SIGNAL add_a1653COUT1_1741 : std_logic;
SIGNAL add_a1696 : std_logic;
SIGNAL add_a1658 : std_logic;
SIGNAL add_a1658COUT1_1755 : std_logic;
SIGNAL add_a1691 : std_logic;
SIGNAL Mux_a10277 : std_logic;
SIGNAL Mux_a10279 : std_logic;
SIGNAL Mux_a10278 : std_logic;
SIGNAL Mux_a10280 : std_logic;
SIGNAL Mux_a10281 : std_logic;
SIGNAL Mux_a10282 : std_logic;
SIGNAL Mux_a10283 : std_logic;
SIGNAL l1_au1_asum_a0 : std_logic;
SIGNAL l2_areduce_nor_a106 : std_logic;
SIGNAL l2_areduce_nor_a107 : std_logic;
SIGNAL l2_areduce_nor_a103 : std_logic;
SIGNAL l2_areduce_nor_a104 : std_logic;
SIGNAL l2_areduce_nor_a105 : std_logic;
SIGNAL l2_al1_acout_a190 : std_logic;
SIGNAL Mux_a10285 : std_logic;
SIGNAL Mux_a10286 : std_logic;
SIGNAL Mux_a10287 : std_logic;
SIGNAL l2_al1_acout_a191 : std_logic;
SIGNAL Mux_a10284 : std_logic;
SIGNAL Mux_a10288 : std_logic;
SIGNAL Mux_a10289 : std_logic;
SIGNAL Mux_a10290 : std_logic;
SIGNAL add_a1663 : std_logic;
SIGNAL add_a1663COUT1_1727 : std_logic;
SIGNAL add_a1686 : std_logic;
SIGNAL add_a1668 : std_logic;
SIGNAL add_a1668COUT1_1714 : std_logic;
SIGNAL add_a1681 : std_logic;
SIGNAL Mux_a10293 : std_logic;
SIGNAL Mux_a10294 : std_logic;
SIGNAL result_t_a16_a : std_logic;
SIGNAL C_a10 : std_logic;
SIGNAL Z_a260 : std_logic;
SIGNAL Z_a259 : std_logic;
SIGNAL Z_a258 : std_logic;
SIGNAL Z_a261 : std_logic;
SIGNAL Z_a262 : std_logic;
SIGNAL Z_a263 : std_logic;
SIGNAL ALT_INV_reset_acombout : std_logic;

BEGIN

ww_OP <= OP;
ww_reset <= reset;
ww_Dinput <= Dinput;
ww_clk <= clk;
ww_write <= write;
ww_sel <= sel;
ww_cin <= cin;
result <= ww_result;
C <= ww_C;
Z <= ww_Z;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
ALT_INV_reset_acombout <= NOT reset_acombout;

clk_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => clk_acombout);

OP_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_OP(1),
	combout => OP_a1_a_acombout);

OP_a2_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",