alu.vho

ALU可以实现16种操作（包括加减乘除移位运算等）

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

-- DATE "05/03/2008 20:33:12"

-- 
-- Device: Altera EP1C6Q240C6 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	ALU IS
    PORT (
	OP : IN std_logic_vector(3 DOWNTO 0);
	reset : IN std_logic;
	Dinput : IN std_logic_vector(15 DOWNTO 0);
	clk : IN std_logic;
	write : IN std_logic;
	sel : IN std_logic;
	cin : IN std_logic;
	result : OUT std_logic_vector(15 DOWNTO 0);
	C : OUT std_logic;
	Z : OUT std_logic
	);
END ALU;

ARCHITECTURE structure OF ALU IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_OP : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_reset : std_logic;
SIGNAL ww_Dinput : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_clk : std_logic;
SIGNAL ww_write : std_logic;
SIGNAL ww_sel : std_logic;
SIGNAL ww_cin : std_logic;
SIGNAL ww_result : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_C : std_logic;
SIGNAL ww_Z : std_logic;
SIGNAL add_a1671 : std_logic;
SIGNAL add_a1676 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL OP_a1_a_acombout : std_logic;
SIGNAL OP_a2_a_acombout : std_logic;
SIGNAL OP_a0_a_acombout : std_logic;
SIGNAL Dinput_a0_a_acombout : std_logic;
SIGNAL reset_acombout : std_logic;
SIGNAL sel_acombout : std_logic;
SIGNAL write_acombout : std_logic;
SIGNAL A_reg_aprocess0_a0 : std_logic;
SIGNAL A_reg_aQ_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a0_a : std_logic;
SIGNAL Mux_a10118 : std_logic;
SIGNAL B_reg_aprocess0_a0 : std_logic;
SIGNAL B_reg_aQ_a0_a : std_logic;
SIGNAL Mux_a10122 : std_logic;
SIGNAL add_a1366 : std_logic;
SIGNAL add_a1361 : std_logic;
SIGNAL Mux_a10123 : std_logic;
SIGNAL Mux_a10292 : std_logic;
SIGNAL Mux_a10124 : std_logic;
SIGNAL cin_acombout : std_logic;
SIGNAL add_a1673 : std_logic;
SIGNAL add_a1673COUT1_1728 : std_logic;
SIGNAL add_a1351 : std_logic;
SIGNAL Dinput_a1_a_acombout : std_logic;
SIGNAL add_a1678 : std_logic;
SIGNAL add_a1678COUT1_1742 : std_logic;
SIGNAL add_a1356 : std_logic;
SIGNAL Mux_a10120 : std_logic;
SIGNAL Mux_a10121 : std_logic;
SIGNAL Mux_a10119 : std_logic;
SIGNAL OP_a3_a_acombout : std_logic;
SIGNAL Mux_a10125 : std_logic;
SIGNAL B_reg_aQ_a1_a : std_logic;
SIGNAL A_reg_aQ_a1_a : std_logic;
SIGNAL add_a1363 : std_logic;
SIGNAL add_a1363COUT1_1702 : std_logic;
SIGNAL add_a1386 : std_logic;
SIGNAL add_a1353 : std_logic;
SIGNAL add_a1353COUT1_1729 : std_logic;
SIGNAL add_a1371 : std_logic;
SIGNAL add_a1358 : std_logic;
SIGNAL add_a1358COUT1_1743 : std_logic;
SIGNAL add_a1376 : std_logic;
SIGNAL Mux_a10126 : std_logic;
SIGNAL Mux_a10127 : std_logic;
SIGNAL Mux_a10128 : std_logic;
SIGNAL add_a1368 : std_logic;
SIGNAL add_a1368COUT1_1715 : std_logic;
SIGNAL add_a1381 : std_logic;
SIGNAL Mux_a10129 : std_logic;
SIGNAL Dinput_a2_a_acombout : std_logic;
SIGNAL l2_al1_au1_asum_a1_a : std_logic;
SIGNAL l1_au1_asum_a1_a : std_logic;
SIGNAL Mux_a10130 : std_logic;
SIGNAL Mux_a10131 : std_logic;
SIGNAL Mux_a10132 : std_logic;
SIGNAL Mux_a10133 : std_logic;
SIGNAL Mux_a10134 : std_logic;
SIGNAL Mux_a10135 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a61 : std_logic;
SIGNAL Mux_a10136 : std_logic;
SIGNAL Mux_a10137 : std_logic;
SIGNAL B_reg_aQ_a2_a : std_logic;
SIGNAL A_reg_aQ_a2_a : std_logic;
SIGNAL add_a1388 : std_logic;
SIGNAL add_a1388COUT1_1703 : std_logic;
SIGNAL add_a1406 : std_logic;
SIGNAL Dinput_a3_a_acombout : std_logic;
SIGNAL l2_al1_au1_ac2_a56 : std_logic;
SIGNAL l2_al1_au1_atemp3_a37 : std_logic;
SIGNAL l2_al1_au1_asum_a2_a : std_logic;
SIGNAL l1_au1_ac2_a7 : std_logic;
SIGNAL l1_au1_asum_a2_a : std_logic;
SIGNAL Mux_a10140 : std_logic;
SIGNAL Mux_a10141 : std_logic;
SIGNAL add_a1383 : std_logic;
SIGNAL add_a1383COUT1_1716 : std_logic;
SIGNAL add_a1401 : std_logic;
SIGNAL Mux_a10142 : std_logic;
SIGNAL add_a1373 : std_logic;
SIGNAL add_a1373COUT1_1730 : std_logic;
SIGNAL add_a1391 : std_logic;
SIGNAL Mux_a10138 : std_logic;
SIGNAL add_a1378 : std_logic;
SIGNAL add_a1378COUT1_1744 : std_logic;
SIGNAL add_a1396 : std_logic;
SIGNAL Mux_a10139 : std_logic;
SIGNAL Mux_a10143 : std_logic;
SIGNAL Mux_a10144 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a2_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a63 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a63COUT1_107 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a66 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a70 : std_logic;
SIGNAL Mux_a10145 : std_logic;
SIGNAL Mux_a10146 : std_logic;
SIGNAL Mux_a10147 : std_logic;
SIGNAL B_reg_aQ_a3_a : std_logic;
SIGNAL A_reg_aQ_a3_a : std_logic;
SIGNAL add_a1403 : std_logic;
SIGNAL add_a1411 : std_logic;
SIGNAL add_a1408 : std_logic;
SIGNAL add_a1426 : std_logic;
SIGNAL add_a1398 : std_logic;
SIGNAL add_a1421 : std_logic;
SIGNAL add_a1393 : std_logic;
SIGNAL add_a1416 : std_logic;
SIGNAL Mux_a10148 : std_logic;
SIGNAL Mux_a10149 : std_logic;
SIGNAL Dinput_a4_a_acombout : std_logic;
SIGNAL l2_al1_au1_ac3_a132 : std_logic;
SIGNAL l2_al1_au1_asum_a3_a : std_logic;
SIGNAL result_t_a34 : std_logic;
SIGNAL l1_au1_ac3_a84 : std_logic;
SIGNAL l1_au1_ac3_a83 : std_logic;
SIGNAL l1_au1_asum_a3_a : std_logic;
SIGNAL Mux_a10150 : std_logic;
SIGNAL Mux_a10151 : std_logic;
SIGNAL Mux_a10152 : std_logic;
SIGNAL Mux_a10153 : std_logic;
SIGNAL Mux_a10154 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a3_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a2_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a68 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a68COUT1_108 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a71 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a61 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a72 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a72COUT1_121 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a75 : std_logic;
SIGNAL Mux_a10155 : std_logic;
SIGNAL Mux_a10156 : std_logic;
SIGNAL Mux_a10157 : std_logic;
SIGNAL B_reg_aQ_a4_a : std_logic;
SIGNAL A_reg_aQ_a4_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a4_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a3_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a73 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a73COUT1_109 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a76 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a2_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a63 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a63COUT1_107 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a66 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a77 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a77COUT1_122 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a80 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a84 : std_logic;
SIGNAL Mux_a10165 : std_logic;
SIGNAL Mux_a10166 : std_logic;
SIGNAL add_a1418 : std_logic;
SIGNAL add_a1418COUT1_1731 : std_logic;
SIGNAL add_a1431 : std_logic;
SIGNAL add_a1423 : std_logic;
SIGNAL add_a1423COUT1_1745 : std_logic;
SIGNAL add_a1436 : std_logic;
SIGNAL Mux_a10158 : std_logic;
SIGNAL Mux_a10159 : std_logic;
SIGNAL add_a1428 : std_logic;
SIGNAL add_a1428COUT1_1704 : std_logic;
SIGNAL add_a1446 : std_logic;
SIGNAL add_a1413 : std_logic;
SIGNAL add_a1413COUT1_1717 : std_logic;
SIGNAL add_a1441 : std_logic;
SIGNAL Dinput_a5_a_acombout : std_logic;
SIGNAL l2_al1_au1_ag_a243 : std_logic;
SIGNAL l2_al1_au1_ag_a242 : std_logic;
SIGNAL l2_al1_au1_ag_a1 : std_logic;
SIGNAL l2_al1_au1_atemp3_a0 : std_logic;
SIGNAL l2_al1_au1_ag_a244 : std_logic;
SIGNAL l2_al1_ac8_a26 : std_logic;
SIGNAL l2_al1_au2_asum_a0_a : std_logic;
SIGNAL l1_au1_ag_a186 : std_logic;
SIGNAL l1_au1_ag_a184 : std_logic;
SIGNAL result_t_a35 : std_logic;
SIGNAL l1_au1_ag_a5 : std_logic;
SIGNAL l1_au2_asum_a0_a : std_logic;
SIGNAL Mux_a10160 : std_logic;
SIGNAL Mux_a10161 : std_logic;
SIGNAL Mux_a10162 : std_logic;
SIGNAL Mux_a10163 : std_logic;
SIGNAL Mux_a10164 : std_logic;
SIGNAL Mux_a10167 : std_logic;
SIGNAL B_reg_aQ_a5_a : std_logic;
SIGNAL A_reg_aQ_a5_a : std_logic;
SIGNAL add_a1443 : std_logic;
SIGNAL add_a1443COUT1_1718 : std_logic;
SIGNAL add_a1451 : std_logic;
SIGNAL add_a1433 : std_logic;
SIGNAL add_a1433COUT1_1732 : std_logic;
SIGNAL add_a1456 : std_logic;
SIGNAL add_a1438 : std_logic;
SIGNAL add_a1438COUT1_1746 : std_logic;
SIGNAL add_a1461 : std_logic;
SIGNAL Mux_a10168 : std_logic;
SIGNAL Mux_a10169 : std_logic;
SIGNAL l2_al1_au2_atemp4_a56 : std_logic;
SIGNAL l2_al1_au2_ac1_a4 : std_logic;
SIGNAL l2_al1_au2_asum_a1_a : std_logic;
SIGNAL l1_au2_ac1_a8 : std_logic;
SIGNAL l1_au2_asum_a1_a : std_logic;
SIGNAL Mux_a10170 : std_logic;
SIGNAL Dinput_a6_a_acombout : std_logic;
SIGNAL Mux_a10171 : std_logic;
SIGNAL Mux_a10172 : std_logic;
SIGNAL add_a1448 : std_logic;
SIGNAL add_a1448COUT1_1705 : std_logic;
SIGNAL add_a1466 : std_logic;
SIGNAL Mux_a10173 : std_logic;
SIGNAL Mux_a10174 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a5_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a1_a_a4_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a78 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a78COUT1 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a81 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a2_a_a3_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a3_a_a2_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a68 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a68COUT1_108 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a71 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a82 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a82COUT1_123 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a85 : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a61 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a86 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_asub_par_add_aadder_a0_a_aadder_aresult_node_acs_buffer_a0_a_a89 : std_logic;
SIGNAL Mux_a10175 : std_logic;
SIGNAL Mux_a10176 : std_logic;
SIGNAL Mux_a10177 : std_logic;
SIGNAL B_reg_aQ_a6_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a6_a_a0_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a5_a_a1_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a4_a_a2_a : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a63 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a63COUT1_107 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_aadder_a2_a_aadder_aresult_node_acs_buffer_a0_a_a66 : std_logic;
SIGNAL mult_rtl_0_amult_core_apadder_asub_par_add_aadder_a1_a_aadder_aresult_node_acs_buffer_a0_a_a70 : std_logic;
SIGNAL A_reg_aQ_a6_a : std_logic;
SIGNAL mult_rtl_0_amult_core_adecoder_node_a0_a_a6_a : std_logic;